【正文】 [ ], DQS Ramaxel Technology Limited Ramaxel Technology Limited Confidential DRAM Interface ? All signals go from the host to the memory except DQS and data which are bidirectional. Ramaxel Technology Limited Ramaxel Technology Limited Confidential Read Cycle ? Typical Read Cycle – Burst Length 4 – CAS Latency = 3 ``S e t u p Tim eH o ld Tim eC A S L a t e n c yC LKC ASD QSD AT AD Q S d e la y e d t o sim u la t e w h a t t h e N V c o n t r o lle r d o e s.Ramaxel Technology Limited Ramaxel Technology Limited Confidential Write Cycle ? Typical Write Cycle – Burst Length 4 – Write latency is always zero ``Setu p Tim eH o ld Tim eC LKC ASD QSD AT ARamaxel Technology Limited Ramaxel Technology Limited Confidential Data Clocking ? CLK is always driven by the host ? DQS is driven by whoever is driving the data – NV chip drives on write cycles – Memory chip drives on read cycles ? This scheme is called ―sourcesynchronous clocking‖ ? Eliminates a lot of the timing headaches from SDR – Adds margin Ramaxel Technology Limited Ramaxel Technology Limited Confidential Latencies ? All kinds – Activate to Precharge – Last write data to precharge – Activate to Read – Activate to Write – Refresh cycle time – Refresh interval – Minimum row active time – Yadda yadda yadda – Controlled by PFB_TIMING0, PFB_TIMING1, PFB_TIMING2 Ramaxel Technology Limited Ramaxel Technology Limited Confidential Write Cycle Ramaxel Technology Limited Ramaxel Technology Limited Confidential DLLs ? A DLL is a DelayLocked Loop – No transistor can switch in zero time, so there will be a delay between clock and DQS on reads – But, it would make it easier if DQS was always in phase with clock. ? DLLoff clockDQS delay not in the spec ? Varies between memory vendors ? Recreates a delayed version of its input clock – Keeps DQS on reads aligned with clocks – It‘s an analog circuit and is sensitive to noise – Can lose lock on the input clock if the signal is not clean or the DLL power supply is noisy. Ramaxel Technology Limited Ramaxel Technology Limited Confidential DLLs ? DLL on ? DLL off C LKD QSD AT AC ASC LKD QSD AT AC ASD Q S d e la y e d t o sim u la t e w h a t t h e N V c o n t r o lle r d o e s.D Q S d e la y e d t o sim u la t e w h a t t h e N V c o n t r o lle r d o e s.Ramaxel Technology Limited Ramaxel Technology Limited Confidential ??? tAA, tAC, tOH ??? tRCD, tRP ??? Setup / Hold time ??? Vih, Vil ??? Voh, Vol ??? Ioh, Iol Timing Parameters Ramaxel Technology Limited Ramaxel Technology Limited Confidential SDRAM Timing Diagram Ramaxel Technology Limited Ramaxel Technology Limited Confidential tAA ,tAC, tOH(SDRAM) Ramaxel Technology Limited Ramaxel Technology Limited Confidential Setup/hold time ? Timing for latching data in Input buffer ??? CLK rising edge is strobe for data ( SDRAM ) ??? DQS rising amp。 falling edge is strobe for data(DDR SDRAM) ??? During Setup amp。 time, there is no abnormal signal allowed Ramaxel Technology Limited Ramaxel Technology Limited Confidential VIH/VIL Ramaxel Technology Limited Ramaxel Technology Limited Confidential VOH/VOL Ramaxel Technology Limited Ramaxel Technology Limited Confidential IOH/IOL Ramaxel Technology Limited Ramaxel Technology Limited Confidential DC Spec Ramaxel Technology Limited Ramaxel Technology Limited Confidential Thanks!