【正文】 t, fast, lowpower, successive approximation ADCs all in the one AD7656 core operates from a single to V power supply and features throughput rates up to 250kSPS. The parts contain low noise, wide bandwidth trackandholdamplifiers that can handle input frequencies up to 8 conversion process and data acquisition are controlled using CONVST signals and an internal oscillator. Three CONVST pins allow independent simultaneous sampling of the three ADC pairs. The AD7656 have both a high speed parallel and serial interface allowing the devices to interface with microprocessors or DSPs. When in Serialinterface mode these parts have a Daisy Chain feature allowingmultiple ADCs to connect to a single serial interface. The AD7656 can acmodate true bipolar inputsignals in the 177。10V range and 177。5V range. It contains a internal reference and can also accept an external reference. If a 3V external reference is applied to the VREF pin, the ADCs canacmodate a true bipolar 177。12V analog input range. VDD andVSS supplies of 177。12V are required for this 177。12V input range.Pin Function DescriptionsREFCAPA, REFCAPB,REFCAPC：Decoupling capacitors are connected to these pins to decouple the reference buffer for each ADC pair. Each REFCAP pin should be decoupled to AGND using 10 μF and 100 nF capacitors.V1 – V6：Analog Input16. These are six singleended Analog inputs. The Analog input range on these channels is ddetermined by the RANGE pin.AGND：Analog Ground. Ground reference point for all analog circuitry on the AD7658/AD7657/AD7656. All analog input signals and any external reference signal should be referred to this AGND voltage. All eleven of these AGND pins should be connected to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than V apart, even on a transient basis.DVCC：Digital Power. Normally at 5V. The DVCC and AVCC voltages should ideally be at the same potential and must not be more than V apart even on a transient basis. This supply should be decoupled to DGND. 10 μF and 100 nF decoupling capacitors should be placed on the DVCC pin.CONVSTA, B, C：Conversion Start Input A,B,C. Logic Inputs. These inputs are used to initiate conversions on the ADC pairs. CONVSTA is used to initiate simultaneous conversions on V1 and V2. CONVSTB is used to initiate simultameous conversions on V3 and V4. CONVSTC is used to initiate simultaneous conversions on V5 and V6. When CONVSTX switches from low to high the trackandhold switch on the selected ADC pairs switches from track to hold and the conversion is initiated./CS：Chip Select. Active low logic input. This input frames the data transfer. When both /CS and /RD are logic low in parallel mode the output bus is enabled and the conversion result is output on the Parallel Data Bus lines. When both /CS and WR are logic low in parallel mode DB[15:8] are used to write data to the onchip control register. In serial mode the /CS is used to frame the serial read transfer./RD：Read Data. When both /CS and /RD are logic low in parallel mode the output bus is enabled. In serial Mode the /RD line should be held low.BUSY：BUSY Output. Transitions high when a conversion is started and remains high until the conversion is plete and the conversion data is latched into the Output Data registers.SER/PAR：Serial/parallel selection Input. When low, the parallel port is selected. When high the serial interface mode is selected. In serial mode DB[10:8] take on their SDATA [C:A] function, DB[0:2] take on their DOUT select function, DB[7] takes on its DCEN function. In serial mode DB15 and DB[13:11] should be tied to DGND.DB[0]/SEL A：Data Bit [0]/Select DOUT A. When SER/PAR = 0, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1, this pin takes on its SEL A function, it is used to configure the serial interface. If this pin is 1, the serial interface will operate with one/two/three DOUT ouput pins and enables DOUT A as a serial output. When operating in serial mode this pin should always be = 1.DB[1]/SEL B：Data Bit [1]/Select DOUT B. When SER/PAR = 0, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1, this pin takes on its SEL B function, it is used to configure the serial interface. If this pin is 1, the serial interface will operate with two/three DOUT ouput pins and enables DOUT B as a serial output. If this pin is 0 the DOUT B is not enabled to operate as a serial Data Output pin and only one DOUT output pin is used.DB[2]/SEL C：Data Bit [2]/Select DOUT C. When SER/PAR = 0, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1, this pin takes on its SEL C function, it is used to configure the serial interface. If this pin is 1, the serial interface will operate with three DOUT ouput pins and enables DOUT C as a serial output. If this pin is 0 the DOUT C is not enabled to operate as a serial Data Output pin.DB[3]/DCIN C：Data Bit [3]/Daisy Chain in C. When SER/PAR =0, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input C.DB[4]/DCIN B：Data Bit [4]/Daisy Chain in B. When SER/PAR =0, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input B.DB[5]/DCIN A：Data Bit [5]/Daisy Chain in A. When SER/PAR is low, this pin acts as a threestate Parallel Digital Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input A.DB[6]/SCLK：Data Bit [6[/Serial Clock. When SER/PAR =0, this pin acts as threestate Parallel Digital Output pin. When SER/PAR =1 this pin takes on its SCLK input function, obtaining the read serial clock for the serial transfer.DB[7]/HBEN/DCEN：Data bit 7/ High Byte Enable/ Daisy Chain Enable. When operating i