【正文】 provides temporal information about the SW task executions, the HW resource usage, the contentions on the munication devices and their impact on the task executions. The results are summarized in a HW resource utilization table and statistical information about the execution time (delays, jitter) for each task. Based on this information, the designers can see how the HW and SW ponents interact and identify eventual bottlenecks in the system.The ASyMod tool can evaluate several different HW architectures and SW implementations against the design constraints. It enables quick and efficient designspace exploration in the early stages of the design process. The tool can be used as in standalone form or incorporated into the system design toolchain by means of importing an abstract system model and exporting the modelevaluation results in the XML (Extensible Markup Language) format.. ASyMod metamodelEmbedded systems in ASyMod are presented in three aspects (SW functionality, HW architecture, and mapping). Each of these aspects is defined by the ASyMod metamodel and each aspect can be represented by a suitablegraph. A simplified metamodel is presented in Fig. 3. The elements visible in each aspect are denoted with dashed lines.An eventflow graph (EFG) is a directed graph that represents an event dependency between the elements, where the graph nodes represent eventdependent elements and the graph edges represent event paths. The nodes can produce and consume events.An architecture graph (AG) is a graph that represents a basic architectural topology and where the graph nodes represent architectural ponents and the edges represent connections between the architectural ponents. A mapping graph (MG) is a directed graph that defines which functionality will be executed on a particular architectural ponent.Model A in ASyMod can be presented as a set A(FG, AG, MG), where FG is an EFG that represents the SW functionality aspect of the ASyMod model, AG is an AG that represents the HW architecture aspect of the ASyMod model and MG is an MG that represents the mapping aspect of the ASyMod model.. Eventflow graph in ASyModIn ASyMod the SW model is presented within the functionality aspect with an EFG graph. The EFG FG can be expressed as a triple FG(S, TA, Xs), where S={sA1, . . . , sAn} is a set of periodic event generators (PEG), TA={tA1, . . . , tAn} is a set of tasks and Xs = {xs1, . . . , xsn} is a set of connections that define the event flow. The tasks and PEGs represent the nodes of the EFG and the connections represent its edges. PEGs periodically generate events and they can be expressed with the pair sAn (STAn, SDAn ), where STAn defines the period of events and SDAn is the initial delay of the first event. PEGs can also be used for generating onetime events. In this case, a very long period STAn should be set (beyond the total simulation time) and the delay SDAn is used to define when an event should be generated. The ASyMod tasks are eventtriggered tasks. An ASyMod task is posed of a description of the HW resource usage for a particular piece of the code and RT execution constraints for the deadline and priority. The task can be expressed with a triple tAn (DAn , LAn , BAn ), where DAn is the task deadline, LAn is the task priority and the boolean BAn defines whether the scheduler should be called at the end of the task execution. This is discussed in more detail in Subsection with a guideline (v). The task execution can begin if the task is triggered with an event and if the scheduler, based on the scheduling policy and task RT execution constraints, allows its execution. After the task execution is finished, the task generates an event. The task can be triggered by a PEG or by an event generated at the end of the execution of some other task. The connections in a set Xs ((TA TA) ∪ (S TA)) define the event flow. Events can be produced by PEGs and by tasks and consumed only by tasks. Each connection is defined with the pair xsn(ym, tAn ), where ym defines the event producer (task tAm or PEG xsm) and tAn is the event consumer task. If a task is triggered by another task, this can be recognized as a sequence of tasks. The period of their execution depends on the PEG that triggers the first task in this sequence. Depending on this PEG, the tasks in the sequence can be onektime or periodically triggered.. Architecture graph in ASyModIn ASyMod the HW architecture is defined with a concept of abstract execution units and abstract munication units and information about how these ponents are connected together. The HW ponents that perform some data putation (., processors, multipliers, filters, etc.) are modelled as execution units, while the ponents that perform data transfer and storage (memories, buses, channels) are modelled as munication units. For plete information about the HW topology, the connections between them must also be defined. AG can be expressed as a triple AG(E, B, Xh), where E = {e1, . . . ,en} is a set of execution units, B = {b1,. . . ,bn} is a set of munication units and Xh = {xh1, . . . ,xhn} (E B) is a set of connections that define the architecture topology. The execution and munication units represent the nodes of AG, while the connections represent its edges. The execution units can be expressed with the pair en(SchAn , PreAn ), where SchAn defines the scheduler algorithm type from a predefined set {None, RM, DM, EDF} and the boolean PreAn defines whether task executions can be preempted. The different execution units in the model can use different scheduling and preemption policies. If the execution unit represents some primary HW ponent (., the MultiplyandAccumulate (MAC) unit, the FIR filter) it cannot schedule its tasks and, consequently, the parameter SchAn for this particular unit should be set to ‘‘None’’. For execution units that represent processors this parameter is set according to the selected scheduling policy