工藝技術(shù)薄膜工藝－淀積-資料下載頁
2025-04-28 01:33本頁面
【正文】 ate: 100 to 300 sccm Pressure: 100 mTorr Temperature: 400 degrees C. Confidential 小 結(jié) ? 薄膜特性要求 ? CVD反應(yīng)步驟和原理 ? CVD分類 APCVD、 LPCVD、 PECVD ? CVD淀積不同材料 si 、 sio 多晶硅、氮化硅、金屬 Confidential CMOS n/pwell Formation Grow Thin Oxide Deposit Nitride Resist silicon substrate UV Exposure Develop Resist Etch Nitride nwell ImplantRemove Resist Confidential silicon substrate pwell nwell Grow Gate Oxide CMOS Transistor Fabrication Deposit PolySi PolySi Implant polySi polySi Resist UV Exposure Develop ResistEtch PolySi Remove Fox Confidential silicon substrate pwell nwell CMOS Contacts amp。 Interconnects Deposit BPTEOS BPTEOS BPSG Reflow Planarization Etchback Resist UV Exposure Develop Resist Contact Etchback Remove Fox polySi polySi n+ n+ p+ p+ Confidential silicon substrate pwell nwell CMOS Contacts amp。 Interconnects Depost Metal 1 Metal 1 it Resist UV Exposure Develop Resist Etch Metal 1 Remove Fox polySi polySi p+ p+ n+ n+ BPTEOS Confidential silicon substrate pwell nwell CMOS Contacts amp。 Interconnects Deposit IMD 1 IMD1 SOG SOG Planarization Etchback Resist UV Exposure Develop ResistVia Etch Remove Fox polySi polySi p+ p+ Metal 1 n+ n+ BPTEOS Confidential silicon substrate pwell nwell CMOS Contacts amp。 Interconnects Deposit Metal 2 Metal 2 Metal 2 Resist UV Exposure Develop Resist Etch Metal 2 Remove Passivation Fox polySi polySi p+ p+ Metal 1 n+ n+ BPTEOS IMD1 SOG Passivation
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