imageprocessingonthetms320c6xvliwdsp-資料下載頁(yè)
【導(dǎo)讀】IMAGEPROCESSING. ONTHETMS320C6X. VLIWDSP. Prof.BrianL.Evans. MageshValliappan. Austin,TX78712-1084. 2. Outline. Introduction. 2-DFIRfilters. Assembler,Cpiler,andsimulator. Developmentboards. Conclusion. 3. Introduction. Architecture. RISCinstructionset. Byteaddressing. Moduloaddressing. Applications. xDSLmodems. Nobitreversed. addressing. Videoconferencing. Documentprocessing. 4. Introduction. Arithmetic. ABS. ADD. ADDA. ADDK. ADD2. MPY. MPYH. NEG. SMPY. SMPYH. SADD. SAT. SSUB. SUB. SUBA. SUBC. SUB2. ZERO. Logical. AND. CMPEQ. CMPGT. CMPLT. NOT. OR. SHL. SHR. SSHL. XOR. Bit. Management. CLR. EXT. LMBD. NORM. SET. Data. Management. LD. MV. MVC. MVK. MVKH. ST. Program. Control. B. IDLE. NOP. C6xInstruction. SetbyCategory. 5. Introduction. .SUnit. ADDNEG. ADDKNOT. ADD2OR. ANDSET. BSHL. CLRSHR. EXTSSHL. MVSUB. MVCSUB2. MVKXOR. MVKHZERO. .LUnit. ABSNOT. ADDOR. ANDSADD. CMPEQSAT. CMPGTSSUB. CMPLTSUB. LMBDSUBC. MVXOR. NEGZERO. NORM. .MUnit. MPYSMPY. MPYHSMPYH. .DUnit. ADDST. ADDASUB. LDSUBA. MVZERO. NEG. Other. NOPIDLE. 6. 2-DFIRFilter. Differenceequation. y(n)=2x(n1,n2)+3x(n1-1,n2)+x(n1,n2-1)+x(n1-. 1,n2-1). 1. 0. 221121. 1. 0. 21. 1. 1. 2. 2. M. m. M. m. mnmnxmmanny. Flowgraph. 000. 021. 031. a(m1,m2)x(n1,n2). m2. m1. n2. n1. 7. sequentialmemory(vector)oflengthM=M1M2. image. Implementation. 123. Throughput. 121.5. Datareadat. onetime. 112. Rasterscan. 8. 2-DFIRImplementation#1onC6x. ;registers:A5=&a(0,0)B5=&x(n1,n2)B7=MA9=M2B8=N2. fir2d1MV.D1A9,A2;innerproductlength. ||SUB.D2B8,B7,B10;offsettonextrow. ||B7,A9,A1;A1=nomorerowstodo. ||SUB.S2B7,A9,B7;numberoftapsleft. fir1LDBU.D1*A5++,A6;loada(m1,m2),zerofill. ||LDBU.D2*B5++,B6;loadx(n1-m1,n2-m2). ||MPYU.M1XA6,B6,A3;A3=a(m1,m2)x(n1-m1,n2-m2). ||ADD.L1A3,A4,A4;y(n1,n2)+=A3. ||[A2]B.S2fir1;ifA2!=0,thenbranch. MV.D1A9,A2;innerproductlength. ||B7,A9,A1;A1=nomorerowstodo. A1]B.S1fir1;outerloop. ||SUB.S2B7,A9,B7;countn
【正文】 s ? Uses TI C piler and assembler ? Probe point support for file I/O ? Realtime data exchange (JTAG) 20 KB/s for C6x ? Scripting language to add new GUI features ? Free training available from San Jose office 18 Development Boards ? Daytona Spectrum Signal C6x Board ? 2 200MHz TMS320C6201 VLIW DSPs (3200 MIPS) ? 32 kB shared dualport RAM for message passing ? 512 kB of Synchronous Burst SRAM per processor ? 16 MB of Synchronous DRAM per processor ? Processor Expansion Module provides 400 MB/s ? Hurricane PCI bridge ? DSP~LINK3 I/O interface from processor Node A ? 19 Spectrum Daytona C6x Board PEM Processor Expansion Module PMC PCI Mezzanine Card 20 TI C6x Evaluation Module ? 133MHz C6201 ? 256 kB 133MHz BSRAM ? 8 Mb 100MHz SDRAM ? PCI bridge ? JTAG ? 16bit audio DAC 21 Conclusion ? Bottleneck for multimedia applications on C6x is bit stream parsing and variablelength decoding ? Bit management routines are only available on S unit ? 7580% execution time for JPEG ? 50% execution time for baseline MPEG4 decoding ? Integrated development environments ? Texas Instruments Code Composer ? Spectrum Signal extensions to Microsoft Visual C++ ? C6x benchmarking for speech/audio applications ? D. Talla, L. K. John, V. Lapinskii, and B. L. Evans, “Performance of Signal Processing and Multimedia Applications on SIMD, VLIW, and Superscalar Arch.,” 1999 IEEE/ACM Microarchitecture Sym., submitted. 22 Conclusion ? Web resources ? newsgroup: FAQ ? embedded processors and systems: ? online courses and DSP boards: ? TI C6x benchmarks: ? References ? R. Bhargava, R. Radhakrishnan, B. L. Evans, and L. K. John, “Evaluating MMX Technology Using DSP and Multimedia Applications,” Proc. IEEE Sym. Microarchitecture, pp. 3746, 1998. ? B. L. Evans, “EE379K17 RealTime DSP Laboratory,” UT Austin. ? B. L. Evans, “EE382C Embedded Software Systems,” UT Austin.
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