[工學]數(shù)字電子技術(shù)課件lec-資料下載頁
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【正文】 cteristics I. Propagation Delay Time 。，，：5nsiss e r i e s7 4 A H C10nsiss e r i e s7 4 H 。,.2。,.1P L HP H LP L HP H LDDLLONLItttandta f f e c tVCa f f e c t e dd i s c h a r g ec h a r g eCl a r g eRd i s c h a r g ec h a r g eCCR e a s o n?????Average propagation delay denoted as tpd. Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 36 二、 AC Noise Margin 交流噪聲容限 Because of load cap and MOS transistor parasitic cap, input signal must have sufficient peak value change and time duration to let output state change. So inverter receiving pulse width close to tpd has much larger noise margin than DC NM. Propagation delay is related to power source, the higher the voltage, the larger the delay, so AC noise margin is larger, see right side figure. Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 37 III. Dynamic Power Dissipation .i g n o r e dbec a noned y n a m i cw i t hc o m p a r e dl i t t l ev e r yisnd i s s i p a t i os t a t i c，)(1,.12143? ????tttt TTT A VT A VDDTdtidtiTIIVPnd i s s i p a t i oonConsists of two parts: 1) on dissipation； 2) load capacitor chargingdischarging dissipation. Practical formula PT=CPDfV2DD 功耗電容 Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 38 III. Dynamic Power Dissipation 221,.2DDLCNLIPLDDICfVCPisndi s s i pat i oav e r aget heiisc ur r e ntdi s c har geTt hr oughCvw he niisc ur r e ntCc har geTt hr oughVvw he nPndi s s i pat i ogdi s c har gi nc har gi ngc apac i t orl oad??????，2)(.3DDLPDCTD fVCCPPPnd i s s i p a t i od y n a m i cT o t a l????Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 39 CMOS inverter dynamic/static dissipation ex. Calculate CMOS inverter total dissipation PTOT. Given VDD=5V， static source current IDD=1uA， load capacitor CL=100pF， CPD=20pF。 Input signal close to ideal square waveform. Frequency f=100 kHz. solution：dynamic mWWfVCCP DDLPDD)(5101 0 010)1 0 020()(23122??????????Static ： mWWVIPDDDDS 0 0 )(510 6 ???? ?So, PTOT is： mWPPPSDT O T ???Conclusion： generally, PS is much less than PD, and can be ignored. Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 40 Summary of Lecture 26 1. 由二極管構(gòu)成的門電路因為有電平偏移、帶負載能力差等缺點只用于 IC內(nèi)部邏輯； 2. 從結(jié)構(gòu)上看 MOS管有 P溝道和 N溝道；從溝道形成的方式不同又分為增強型和耗盡型 MOS管； 3. MOS管為電壓控制器件，其靜態(tài)輸入電流為 0。輸出電流 iD在輸出特性的不同區(qū)域變化規(guī)律不同。在截止區(qū)等于 0，在恒流區(qū)只受柵極電壓的控制，在可變電阻區(qū)與漏源電壓近似成線性關(guān)系； 4. CMOS是互補對稱的 MOS器件， CMOS反相器在靜態(tài)狀況下總是有一個管截止，另一個管導通，因而靜態(tài)功耗很低； 5. CMOS反相器在動態(tài)情況下其功耗與輸入電壓的頻率成正比。同時交流噪聲容限比直流噪聲容限大很多。 Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 41 The End of Lecture 29 Thank you for your participation! Lecture 29 MOS transistor and CMOS device 2022/3/13 Chapter 12 Integrated Circuit Technologies 42 Class evaluation and problem assignment Two way interactive questionandanswer session. Homework assignment: P482~484, 1, 3, 7, 11, 15 Lecture 29 MOS transistor and CMOS device
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