[理學(xué)]中科大多核并行計(jì)算課件-資料下載頁(yè)
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【正文】 Core 3 Core 4 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache One or more levels of cache Main memory x=15213 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 62 2022/2/16 The cache coherence problem Core 2 reads x Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=15213 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache Main memory x=15213 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 63 2022/2/16 The cache coherence problem Core 1 writes to x, setting it to 21660 Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip assuming writethrough caches 國(guó)家高性能計(jì)算中心（合肥） 64 2022/2/16 The cache coherence problem Core 2 attempts to read x… gets a stale copy Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 65 2022/2/16 Solutions for cache coherence ? This is a general problem with multiprocessors, not limited just to multicore ? There exist many solution algorithms, coherence protocols, etc. ? A simple solution: invalidationbased protocol with snooping 國(guó)家高性能計(jì)算中心（合肥） 66 2022/2/16 Intercore bus Core 1 Core 2 Core 3 Core 4 One or more levels of cache One or more levels of cache One or more levels of cache One or more levels of cache Main memory multicore chip intercore bus 國(guó)家高性能計(jì)算中心（合肥） 67 2022/2/16 Invalidation protocol with snooping ? Invalidation: If a core writes to a data item, all other copies of this data item in other caches are invalidated ? Snooping: All cores continuously “snoop” (monitor) the bus connecting the cores. 國(guó)家高性能計(jì)算中心（合肥） 68 2022/2/16 The cache coherence problem Revisited: Cores 1 and 2 have both read x Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=15213 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache Main memory x=15213 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 69 2022/2/16 The cache coherence problem Core 1 writes to x, setting it to 21660 Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache x=15213 One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip assuming writethrough caches INVALIDATED sends invalidation request intercore bus 國(guó)家高性能計(jì)算中心（合肥） 70 2022/2/16 The cache coherence problem After invalidation: Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 71 2022/2/16 The cache coherence problem Core 2 reads x. Cache misses, and loads the new copy. Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache x=21660 One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip 國(guó)家高性能計(jì)算中心（合肥） 72 2022/2/16 Alternative to invalidate protocol: update protocol Core 1 writes x=21660: Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=21660 One or more levels of cache x=21660 One or more levels of cache One or more levels of cache Main memory x=21660 multicore chip assuming writethrough caches UPDATED broadcasts updated value intercore bus 國(guó)家高性能計(jì)算中心（合肥） 73 2022/2/16 Which do you think is better? Invalidation or update? 國(guó)家高性能計(jì)算中心（合肥） 74 2022/2/16 Invalidation vs update ? Multiple writes to the same location ? invalidation: only the first time ? update: must broadcast each write (which includes new variable value) ? Invalidation generally performs better: it generates less bus traffic 國(guó)家高性能計(jì)算中心（合肥） 75 2022/2/16 DualCore、 SMP、 Cluster 體系結(jié)構(gòu) 特性 SMP（對(duì)稱多處理機(jī)） Cluster（集群） DualCore 處理器 單一主機(jī)，多個(gè)處理器 多臺(tái)主機(jī)，有各自的處理器（一或多） 單一主機(jī)，單一處理器，多個(gè)核心 操作系統(tǒng) 單一 多個(gè) 單一 主要并行計(jì)算方式 多進(jìn)程，內(nèi)存共享 多進(jìn)程，基于消息傳遞 多線程
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