模擬集成電路的設(shè)計(jì)流程-資料下載頁(yè)
2025-01-08 15:09本頁(yè)面
【正文】 tor which must be defined with config view cell name is top circuit name for simulation view name will be set as config Use Create New File to create a new config view with HierarchyEditor 2022/2/4 共 88頁(yè) 74 Set New Configuration Use Template sample information spetreVerilog 1 2 3 3. Change the view name to schematic for simulation 4. Click OK 2022/2/4 共 88頁(yè) 75 Open the Schematic Version of Config View Open the schematic version of the config view of mix from the Library manager 2022/2/4 共 88頁(yè) 76 Set Block Partition 開啟 hierarchy editor 設(shè)定所使用的 cell view 顯示所使用的 cell view 及其顏色設(shè)定 Schematic editor 中 的 HierarchyEditor 及 MixedSignal 兩項(xiàng) Menu是由菜單 ToolsMixed Signal 2022/2/4 共 88頁(yè) 77 Set Block Partition(cont.) 2022/2/4 共 88頁(yè) 78 Check Block Partition Change analog amp。 digital stop views to match the stop views in your hierarchy editor (as below) 2022/2/4 共 88頁(yè) 79 Check Partition Results 設(shè)定顯示的顏色及項(xiàng)目 顯示所有模塊劃分的結(jié)果 顯示模擬電路模塊 顯示數(shù)字電路模塊 顯示混合信號(hào)電路模塊 顯示無(wú)法規(guī)類的電路模塊 清除所有顯示內(nèi)容 2022/2/4 共 88頁(yè) 80 Partition Requirement ? The design must contain at least one analog ponent. ? The design must contain at least one digital ponent. ? There must be with at least one interface . ? Analog stimuli defined in the analog stimuli file cannot be used to drive digital . ? Digital stimuli defined in the digital stimuli file can not be used to drive analog . ? Any interface must be identified before listing. 2022/2/4 共 88頁(yè) 81 Setup the analog/digital interface Select: MixedSignal Interface Elements Instance this tool is used to configure how the digital block reads analog inputs and how digital outputs are seen by analog cells (effective A/D and D/A). 2022/2/4 共 88頁(yè) 82 Setup the analog/digital interface MOS_a2d: A2D_V0 低電平 A2D_V1 高電平 A2D_TX： voltage between V0 and V1 after TX will yield a logic X MOS_d2a： Model Parameters D2A_VL : input low voltage D2A_VH : input high voltage D2A_TR : rise time for low to high D2A_TF : fall time for high to low 2022/2/4 共 88頁(yè) 83 Setup Menu in Analog Environment With Setup window to define simulation initialization setup ?Choose the simulator ?Define device model library ?Define temperature …… 2022/2/4 共 88頁(yè) 84 Choosing Simulator/Directory/Host 選擇 SpectreVerilog 2022/2/4 共 88頁(yè) 85 Choose Analysis Type Invoke the analysis setting window For MixedSignal simulation, only tran is meaningful Set the simulation time Check this box to enable this simulation 2022/2/4 共 88頁(yè) 86 Submit the Simulation Execute the simulation job with Run, or create the list with Netlist start simulation 2022/2/4 共 88頁(yè) 87 Results 其中 clk：數(shù)字模擬輸入 DIGITAL_OUT：數(shù)字輸出 ANALOG_OUT ：模擬輸出 2022/2/4 共 88頁(yè) 88 THANK YOU!
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