dsp56800efamily-資料下載頁
2025-10-03 16:00本頁面
【導讀】120MIPSat120MHz. 24Kx16-bitDataRAM. 1Kx16-bitBootROM. JTAG/EnhancedOn-ChipEmulation(EOnCE)for. TimeofDay. Upto47GPIO. 144pinMAPBGA(MoldArrayProcess-BallGrid. Canbeprogrammedto. Ahardwiredspecific. function(:ESSI,HPI,SCI…etc.SecondaryXDataBus(XDB2). ProgramDataBus(PDB). IPBusinterface. 0=GPIOmode;pinoperationis. 1=Normalmode;pinoperationis. 0=Pinisaninput;pull-upsaredependent. 1=Pinisanoutput;pull-upsaredisabled. 0=Pu
【正文】 ber 17, 2020 Introduction to 5685x Series ? Six independent, functionally equivalent DMA controllers ? Allows transfers from peripheral to data memory or from data memory to peripheral ? DMA transfers are supported by ESSI0, ESSI1, SPI, SCI, and HI ? Each peripheral can generate independent DMA request for transmit and receive, creating 10 possible DMA channels (transmit and receive for five peripherals) ? DMA controllers can be programmed to support any one of possible DMA channels ? Contains configuration register set for specifying source and destination address of transfer and type of address update ? Supports three types of address update: ?No update ?Increment ?Increment modulo ? DMA controller supports configurable block size and maintains word count ? DMA controller can be configured to generate core interrupt, terminate transfers, or do both after block has been transferred Six Channel DMA Controller Ira Fulton School of Engineering Electrical Department EEE408 – Real Time DSP Tuesday, November 17, 2020 Introduction to 5685x Series ?Used to help software recover from runaway code ?Free running counter designed to generate a chip wide reset on overflow ?Software must periodically service COP to clear the counter and prevent a reset under normal conditions Computer Operating (COP) Properly Timer Ira Fulton School of Engineering Electrical Department EEE408 – Real Time DSP Tuesday, November 17, 2020 Introduction to 5685x Series Voltage Reference + + Voltage Level Shifter Voltage Level Shifter Peripheral Power Core Power Digital Ground Analog Ground Reset + + Features: ?The Circuit monitors both the core power supply and peripheral power supply ?Holds a wide chip reset once either of these supply voltages are below the thresholds ?Generate the address of reset vector provided to the core after exit Reset ? The address of reset vector (same as the COP Reset) is located at $1F0000 for 5685x devices Power On Rest (POR) Ira Fulton School of Engineering Electrical Department EEE408 – Real Time DSP Tuesday, November 17, 2020 Introduction to 5685x Series ? Implemented as a sequence of counters to track elapsed time up to 65,536 days. The starting day is determined by application software ? Separate counters for seconds, minutes, hours and days ? Time can be read any time ? Alarm interrupt with independent enable, capturing a designated time ? Module reset only at poweron, unaffected by reset pin, software reset or COP reset ? Capable to generate interrupt, pulling the device out of power saving mode ? A 16bit Clock Scaler Register associated with 7bit prescaler allows wide input clock range: 0 ~ 65536*128 Hz Time of Day (TOD) Timer
教學課件相關推薦
鄂ICP備17016276號-1