【導(dǎo)讀】Introduction. TheChargePump. Non-idealBehavior. ChargeSharing. CurrentMismatch. Summary. Reference. Introduction. TheChargePump. Non-idealBehavior. ChargeSharing. CurrentMismatch. Summary. Reference. phase.Introduction. TheChargePump. Non-idealBehavior. ChargeSharing. CurrentMismatch. Type3:

　　

【正文】 Dual Compension Implementation of a PMOS – NMOS Charge Pump Topology ? Charge Pump Design 4: Low Voltage High Speed Charge Pump design ? Charge Pump Design 5: Charge Pump Design for Ultra Low Power PLL ? Charge Pump Design 6: Charge Pump Design for Low Phase Noise Low Power PLL ? Charge Pump Design 7: A Fully Differential Charge Pump ? Charge Pump Design 8: Charge Pump Design for a Low Power PLL ? Summary ? Reference ? A typical fully differential charge pump topology is as shown in fig. 13 ? It has several advantages over the single – ended topology [1] ? These includes ? Firstly, the switch mismatches between NMOS transistors and PMOS transistors does not substantially affect the overall performance. ? Secondly, the differential charge pump has switches using only NMOS transistors which also helps with the reduction of the current mismatch. ? Thirdly, this configuration doubles the range of the output voltage pliance pared to the singleended charge pump. For lowvoltage operation, the limited output voltage range of the single – ended charge pump makes it difficult for the VCO to meet the specified tuning range unless the VCO gain is increased. ? Fourthly, the differential output stage is less sensitive to leakage current since the leakage current behaves as a monmode offset with the dual output stages. ??? ? Lastly, the differential charge pump with two loop filters provides better immunity to the supply, ground and the substrate noise when onchip loop filters are used. However, these advantages can be achieved at the cost of two loop filters, monmode feedback circuitry and more power dissipation due to the constant current biasing. Fig 13. Schematic of a typical fully differential charge pump topology [7] ? Introduction ? The Charge Pump ? Basic Principle of Operation of a Conventional Charge Pump ? Nonideal Behavior ? Charge Sharing ? Charge Injection and Clock Feedthrough ? Current Mismatch ? Charge pump architectures ? Type 1: Conventional Tristate ? Type 2: Current Steering Topology ? Type 3: Differential Input with Single – Ended Output Topology ? Type 4: Fully Differential Charge Pump Topology ? Type 5: High Voltage Charge Pumps ? Design Considerations ? Typical Charge Pump Designs ? Charge Pump Design 1: Dual Compensation Charge Pump ? Charge Pump Design 2: NMOS Topology for a Dual Compensation Charge Pump Implementation ? Charge Pump Design 3: Dual Compension Implementation of a PMOS – NMOS Charge Pump Topology ? Charge Pump Design 4: Low Voltage High Speed Charge Pump design ? Charge Pump Design 5: Charge Pump Design for Ultra Low Power PLL ? Charge Pump Design 6: Charge Pump Design for Low Phase Noise Low Power PLL ? Charge Pump Design 7: A Fully Differential Charge Pump ? Charge Pump Design 8: Charge Pump Design for a Low Power PLL ? Summary ? Reference ? This type of charge pump gives very high output voltages higher than the supply voltage ? In many applications such as the Power IC, continuous time filters, EEPROMs, and switchedcapacitor transformers, automotive parts, tele interfaces, cellular phones and microelectromechanical systems (MEMS), voltages higher than the power supplies are frequently required. [8], [9] ? Increased voltage levels are obtained in a charge pump as a result of transferring charges to a capacitive load, and do not involve amplifiers or regular transformers. ? The operating supply voltage for high voltage (HV) applications is increasing steadily, ranging from 20V to 300V. ? They can be grouped into the following topologies: The Voltage Doubler Cascade Charge Pump ? This type includes: twophase voltage doubler (TPVD), the Makowski charge pump and the multiphase voltage doubler (MPVD). ? These circuits generally have the best output ripple on the market ? Difficult to implement for higher number of stages ( 10 stages) Dickson Charge Pump [9] ? Dickson charge pump exhibits a linear growth of the number of devices used with the voltage gain level, while the voltage doublers and Makowski charge pumps requirements for the devices grow logarithmically with the voltage gain The Pelliconi Cascade Charge Pump ? It’s gain is higher than the gain of any other additive architecture ? Its uses simple clocking (uses simple 2phase nonoverlapping clock generator). ? Also, its output ripples is parable to the ripple produced by voltage doublers. ? This also exhibits a linear growth in the number of stages, however, since the voltage gain for the Pelliconi architecture is times higher than the gain of a Dickson charge pump, and almost twice that of a single cascade charge pump, the number of stages needed to reach a specific output voltage is reduced. ? Introduction ? The Charge Pump ? Basic Principle of Operation of a Conventional Charge Pump ? Nonideal Behavior ? Charge Sharing ? Charge Injection and Clock Feedthrough ? Current Mismatch ? Charge pump architectures ? Type 1: Conventional Tristate ? Type 2: Current Steering Topology ? Type 3: Differential Input with Single – Ended Output Topology ? Type 4: Fully Differential Charge Pump Topology ? Type 5: High Voltage Charge Pumps ? Design Considerations ? Typical Charge Pump Designs ? Charge Pump Design 1: Dual Compensation Charge Pump ? Charge Pump Design 2: NMOS Topology for a Dual Compensation Charge Pump Implementation ? Charge Pump Design 3: Dual Compension Implementation of a PMOS – NMOS Charge Pump Topology ? Charge Pump Design 4: Low Voltage High Speed Charge Pump design ? Charge Pump Design 5: Charge Pump Design for Ultra Low Power PLL ? Charge Pump Design 6: Charge Pump Design for Low Phase Noise Low Power PLL ? Charge Pump Design 7: A F