【導(dǎo)讀】步進(jìn)電機(jī)因其能夠精確地控制機(jī)械的移動(dòng)量而被廣泛采用。步進(jìn)電機(jī)是由輸入的脈沖信號(hào)來(lái)加以控制的。模擬電路雖然可以用來(lái)產(chǎn)生連續(xù)可調(diào)的脈沖信號(hào)，但卻難以控制，而用數(shù)字集成電路來(lái)對(duì)步進(jìn)電機(jī)進(jìn)行控制，則能克服以上缺點(diǎn)。采用VHDL的設(shè)計(jì)方法有著不依賴器件、移植容易、能加快設(shè)計(jì)的特點(diǎn)。并且，VHDL在現(xiàn)場(chǎng)就能進(jìn)行修改，與FPGA器件相結(jié)合，能大大提高設(shè)計(jì)的靈活性與效率，縮短產(chǎn)品的開發(fā)周期，加快產(chǎn)品的上市時(shí)間。VHDL+FPGA的設(shè)計(jì)方法是數(shù)字系統(tǒng)設(shè)計(jì)的一個(gè)創(chuàng)新，也是未來(lái)的一種發(fā)展方向。步進(jìn)電機(jī)是一種將電脈沖轉(zhuǎn)化為角位移的執(zhí)行機(jī)構(gòu)，已廣泛應(yīng)用于各種自動(dòng)化控制系統(tǒng)中。為了提高對(duì)步進(jìn)電機(jī)的細(xì)分要求，提出了基于FPGA控制的步進(jìn)電機(jī)控制器方案。給出了用VHDL語(yǔ)言層次化設(shè)計(jì)各功能模塊的過(guò)程，利用QuartusⅡ進(jìn)行仿真，給出了仿真結(jié)果，并成功地在FPGA器件上驗(yàn)證了設(shè)計(jì)的可能性。該設(shè)計(jì)硬件結(jié)構(gòu)簡(jiǎn)單可靠，可根據(jù)實(shí)踐需要靈活方便進(jìn)行配置。

　　

【正文】 Output16(14)=39。139。else Output16(14)=39。039。end if。if(Count16(11 downto 0)=100000000000)then Output16(4)=39。139。else Output16(4)=39。039。end if。if(Count16(12 downto 0)=1000000000000)then Output16(3)=39。139。else Output16(3)=39。039。end if。if(Count16(13 downto 0)=10000000000000)then Output16(2)=39。139。else Output16(2)=39。039。end if。if(Count16(14 downto 0)=100000000000000)then Output16(1)=39。139。else Output16(1)=39。039。end if。if(Count16(15 downto 0)=1000000000000000)then Output16(0)=39。139。else Output16(0)=39。039。end if。end if。end process。 process(RESET, KEY, CLK, Output16, swave_out, key_tmp)beginif(RESET=39。039。)then swave_out=39。039。else for i in 0 to 15 loop key_tmp(i)=KEY(i) and Output16(i) and CLK。end loop。 swave_out= key_tmp(0) or key_tmp(1) or key_tmp(2) or key_tmp(3) or key_tmp(4) or key_tmp(5) or key_tmp(6) or key_tmp(7) or key_tmp(8) or key_tmp(9) or key_tmp(10) or key_tmp(11) or key_tmp(12) or key_tmp(13) or key_tmp(14) or key_tmp(15)。end if。end process。end step_wave_arch。附件2 電路圖 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