【導(dǎo)讀】基準電壓源是模擬電路設(shè)計中廣泛采用的一個關(guān)鍵的基本模塊。所謂基準電壓源就是能提供高穩(wěn)定度基準量的電源，這種基準源與電源、工藝參數(shù)和溫度的關(guān)系很小，但是它的溫度穩(wěn)定性以及抗噪性能影響著整個電路系統(tǒng)的精度和性能。本文的目的便是設(shè)計一種基于CMOS帶隙基準電壓源。然后詳細介紹了MOS器件的基本原理、基準電壓源電路原理，并對不同的帶隙基準源結(jié)構(gòu)進行了比較。模擬和仿真結(jié)果表明，電路實現(xiàn)了良好的溫度特性，0℃～100℃溫度范圍內(nèi)，℃，。隨著手提設(shè)備對低電源需求的不斷增加，設(shè)計低壓工作的電壓基準源成為當(dāng)前基準源研究的熱點。采用這些電路結(jié)構(gòu)后主要的工作電壓限制通常來自于運放的工作電壓，不同運放的電路結(jié)構(gòu)和MOS管襯底效應(yīng)造成的高閾值電壓是限制工作電壓的主要因素。

　　

【正文】 tube size is larger, in order to reduce the circuit of the 1/ f noise. Current mirror load tube P5, P6 and difference of N1, N2 wide length is large, to suppress the powerThermal noise road. Due to the resistance in the circuit value is large, so in the process of using a well resistor. Capacitor C0 contributes to the circuit stability, but also can reduce the operational amplifier of the width, helping to reduce the impact of noise.2 The simulation and analysis of the resultsThe simulation of the circuit based on the CSMC process model in Cadence design platform under the Spectre simulator. Temperature characteristic curve, circuit of the DC power supply rejection characteristic curve, PSRR curve, the startup time curve as shown in figure 4. The results of simulation parameters as shown in table 2.table 1 Device parameters circuitponentvalueP1P2P3P4P510um/P610um/P72um/18umN118um/3umN218um/3umN310um/2umN410um/2umN518um/2umN62um/10umQ15um*5umQ240um*5umC020pFR15006kR255kR355kR4Table 2 results of simulation parametersVoltage/Vtemperature /℃temperature coefficient /ppm/℃PSRR/dBrejection characteristics /mV/Vconsumption /uW~410~+1308034516 (~130℃)~ (0~1kHz)(a) the temperature characteristic curve(b) suppression characteristics of DC power supply(c) the exchange of PSR3 PerorationBased on the typical application of CMOS voltage reference source, the prehensive level of temperature pensation, current pensation technique, the bandgap voltage reference circuit design. The power supply operating range of the bandgap reference circuit is ~4V, the working temperature of 10~ + 130 ℃, the reference output voltage is Vref, the temperature coefficient can be reduced to ℃, power supply rejection ratio is 70dB. The simulation results proved the correctness of the design.附錄 C：網(wǎng)表（1）NMOS管的閾值電壓：* vtnliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG 0 0VdcVDS NR 0 3VdcVR NR ND 0M1 ND NG 0 0 nvn W= L=.DC VGS 0 2 .measure DC mvtn when I(vr)= .PRINT dc mvtn.END（2）PMOS管的閾值電壓：* vtpliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG VDD 0VdcVDS 0 VDD 3VdcVR 0 ND 0M1 ND NG VDD VDD nvp W= L=.DC VGS 2 0 .MEAS DC mvtp when I(vr)= .PRINT dc mvtp.END （3）NMOS：a）KPn* source Kpnliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG 0 0VdcVDS NR 0 3VdcVR NR ND 0M1 ND NG 0 0 nvn W= L=.DC VGS 0 2 .PRINT DC ip=PAR(39。sqrt(I(vr))39。).b）* source NMOS lamtaliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG 0 VDS NR 0 0VdcVR NR ND 0M1 ND NG 0 0 nvn W= L= .DC VDS 0 3 .END（4）PMOS：a）KPp* source Kppliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG VDD 0Vdc VDS 0 VDD 3Vdc VR 0 ND 0 M1 ND NG VDD VDD nvp W= L= .DC VGS 2 0 .PRINT DC ip=PAR(39。sqrt(I(vr))39。).ENDb）* source PMOS lamtaliuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST VGS NG VDD VDS 0 VDD 0Vdc VR 0 ND 0 M1 ND NG VDD VDD nvp W= L= .DC VDS 3 0 .END（5）運算放大器* amp.OPTIONS LIST NODE POST *****************************************.lib 39。E:\c\39。 tt****************************************.global Vdd Gnd****************************************.subckt amp vin1 vin2 voutCc 2 9 3pFM1 1 vin1 3 3 nvp L=2u W=4u M=31 M2 2 vin2 3 3 nvp L=2u W=4u M=31 M3 1 1 Gnd Gnd nvn L=2u W=8u M=2 M4 2 1 Gnd Gnd nvn L=2u W=8u M=2 M5 3 4 Vdd Vdd nvp L=2u W=10u M=7 M6 vout 4 Vdd Vdd nvp L=4u W=20u M=28M7 vout 2 Gnd Gnd nvn L=4u W=16u M=16 M8 5 4 Vdd Vdd nvp L=2u W=14u M9 4 4 Vdd Vdd nvp L=2u W=14uM10 5 5 7 Gnd nvn L=2u W=14u M11 4 5 6 Gnd nvn L=2u W=14u M12 7 6 Gnd Gnd nvn L=2u W=14u M13 6 6 8 Gnd nvn L=2u W=16u R1 8 Gnd 1300 R2 9 vout 0 .ends（6）失調(diào)電壓和輸出電壓范圍* measure_ampliuzuowei.OPTIONS LIST NODE POST ****************************************.lib 39。E:\c\39。 tt.include 39。E:\c\39。 ****************************************.global Vdd Gnd****************************************X1 vin1 vin2 vout amp vdd vdd gnd 5vin1 vin1 gnd ac 0vin2 vin2 gnd ac 0.op.dc vin1 .print dc v(vout).end（7）輸入共模范圍* measure_amp2liuzuowei.OPTIONS LIST NODE POST ****************************************.lib 39。E:\c\39。 tt.include 39。E:\c\39。 ****************************************.global Vdd Gnd****************************************Cc 2 9 3pFM1 1 vin1 3 3 nvp L=2u W=4u M=31 M2 2 vin2 3 3 nvp L=2u W=4u M=31 M3 1 1 Gnd Gnd nvn L=2u W=8u M=2 M4 2 1 Gnd Gnd nvn L=2u W=8u M=2 M5 3 4 Vdd Vdd nvp L=2u W=10u M=7 M6 vout 4 Vdd Vdd nvp L=4u W=20u M=28M7 vout 2 Gnd Gnd nvn L=4u W=16u M=16 M8 5 4 Vdd Vdd nvp L=2u W=14u M9 4 4 Vdd Vdd nvp L=2u W=14uM10 5 5 7 Gnd nvn L=2u W=14u M11 4 5 6 Gnd nvn L=2u W=14u M12 7 6 Gnd Gnd nvn L=2u W=14u M13 6 6 8 Gnd nvn L=2u W=16u R1 8 Gnd 1300 TC=, R2 9 vout 0 TC=, vdd vdd gnd 5v1 vin1 vout 0vin2 vin2 gnd ac 0.op.dc vin2 0 5 .print dc ip=par(39。i(m5)39。).end（8）幅頻相頻特性（在不改變輸出管的寬長比的前提下，增加溝道長度，對增益提高有很大作用，對失調(diào)也有好處）* measure_amp3liuzuowei.OPTIONS LIST NODE POST ****************************************.lib 39。E:\c\39。 tt.include 39。E:\c\39。 ****************************************.global Vdd Gnd****************************************X1 vin1 vin2 vout amp vdd vdd gnd 5vin1 vin1 gnd ac 0vin2 vin2 gnd ac 1.op.ac dec 100 1Hz 1000MegHz.print ac vdb(vout) vp(vout).end（9）pnp管Vbe結(jié)的溫度系數(shù)* pnp 1liuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST Q1 Gnd Gnd N1 PNP5 m=1i2 Vdd N1 200uAvdd vdd gnd .DC temp 0 100 i2 50u 200u 50u *.DC temp 0 100 .print v(n5).END（10）pnp管ΔVbe結(jié)的溫度系數(shù)* pnp 2liuzuowei.lib 39。E:\c\39。 tt.OPTIONS LIST NODE POST Q1 Gnd Gnd N2 PNP5 M=1Q2 Gnd Gnd N1 PNP5 M=4i3 Vdd N1 200uAi4 Vdd N2