【導(dǎo)讀】算術(shù)運算、邏輯運算以及控制操作。在外部，CPU為轉(zhuǎn)換指令數(shù)據(jù)和控制信息提供一個。或多個總線并從組件連接到它。在通用計算機開始的第一章，CPU作為處理器的一部分。但是CPU有可能出現(xiàn)在很多電腦之間，小，相對簡單的所謂微控制器的計算。機被用在電腦和其他數(shù)字化系統(tǒng)中，以執(zhí)行限制或?qū)ｉT任務(wù)。在普通電腦的鍵盤和檢測器中，但是這些組件也被屏蔽。這一章中所討論的CPU可能十分不同。字長也許更短，，編制數(shù)。量少，指令集有限。相對而言，性能差，但對完成任務(wù)來說足夠了。最重要的是它的微?？刂破鞯某杀竞艿?，符合成本效益。兩個CPU的性能，并提交了用來提高性能的一些方法的簡要概述。于一般數(shù)字系統(tǒng)設(shè)計的設(shè)計思路。正如我們前一章提到的，一個典型的CPU通常被分成兩部分：數(shù)據(jù)路徑和控制單元。執(zhí)行獲得重要的運行序列。堆棧指針的出現(xiàn)的情況表明內(nèi)。DST，分別是3位的來源登記和目的地登記領(lǐng)域。算或處理是來自注冊。域，其中包括S和SRC，被用于為所有指令的案件。

　　

【正文】 th constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 104(b). We find that, based on the eight shift instructions provided, the shifter from section 810, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the ining bit, and for the left arithmetic shift, 0 is the ining bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flipflop output be provide as an input on both ends of the shifter. The inputs are furnished by two 4t01 multiplexers, MUX R and MUX L, added to a basic 16bit shifter, all shown in Figure 105(a). also, the appropriate end bits from the input operand must be sent to the carry flipflop. A 2to1 multiplexer MUX SO selects the end bit to pass to the carry flipflop C. the symbol for the new shifter, which replaces the basic shifter from section 810, appears in Figure 105(b), FS3, FS2, FS1, and FS0 from the FS field drive the control inputs S3, S2, S1 and S0, respectively. All modifications to the original datapath are represented in Figure 106. As a part of the design process, the new datapath needs to be checked to make sure that it has all of the capabilities necessary for implementing the instruction set and addressing modes .Certainly ,some decisions have been made that have not been discussed. For example, there is no dedicated multiplication or division hardware, so these operations must be implemented by microprograms controlling the datapath. 16 Microprogrammed Control Organization The microgrammed control unit acpanies the datapath of Figure 106 in Figure 107. The control consists of four principal parts. One is the control unit registers : the instruction register IR, the program counter PC, and the stack pointer SP. In some designs the PC and SP are logically included in the register file and thus are a part of the datapath .Here, since they are separate from the register file and are used primarily for program control ,we haveincluded them with the control . Sequencing within the control unit is provides by the microsequencer , which contains two registers: the control address register CAR and the subroutine branch register SBR. The program counter for the microprogram , the CAR simply counts up to the next address in sequence or loads in parallel . With a parallel load , the address can be set to any value and the nextaddress es from three source including the nextaddress field in the current microinstruction. Microroutines have subroutines, just as programs do. To distinguish them, we call subroutines for microprograms microsubroutines. The SBR is used to store the next address for the CAR at the time a microsubroutine in order to return microprogram execution to the 17 next microinstruction in the calling microroutine. The final part of the control unit is the instruction decode, which consists of binational logic and is also a next address source for the CAR. Microprogram structure We approach the microprogram design top down. The top level consists of an ASMlike chart giving a flow of microroutines. These routines have labels similar to the stages in the pipelined CPU in section 811. in this case, however, rather than being performed in a single clock with binational logic, the routines require the use of the same hardware over multiple cycles. The flow between and, to same extent, within the routines is intimately tied to the instructions and their decoding. Since the mapping ROM can be used for branching simultaneously with a format A data transfer or manipulation operation, it is convenient to control the flow between microroutines entirely by using the mapping ROM. This flow is shown in Figure 108。 the chart is not strictly an ASM chart, since each rectangular box corresponds to microroutines representing multiple states rather than a single state and to multiple clock cycles rather than single one. The execution of each instruction begins with the instruction Fetch microroutine. The PC provides the address and is updated to the next address. The instruction fetched is placed in the IR. The the instructiondecoding process begins, using MUX M and the mapping ROM. For MM equal to 00, only the first three bits of OPCODE are used, with the remaining bit set to addition, the third bit from the left ignored except when the first two equal to 01. A fiveway branch results. This branch is represented by the five binary decision boxes in the figure. Since the bits of OPCODE that are used denote the number of operands for the instruction being decoded, the destinations of the branches are, in three cases, microroutines to fetch the operands. In another case, program branch addresses are fetched. In the final case, the branch in the chart goes directly to execution. There are three paths to execution blocks that are dependent upon the decision made by the decision boxes. These paths preserve information from the decoding of the three bits of OPCODE in the Instruction Fetch to obtain the shift amount parameter, there is an additional decision required at the end of the twooperand fetch. In four of the five decisions, an operand fetch routine is performed. Depending upon the first three bits of OPCODE, either a single operand, two operands (or one operand plus a parameter), or a branch address is fetched. The operand address, and parameter values are placed in locations reserved for them in registers R12 through R15 (SA, SD, DA, and DD). The four execution routines find the operands and addresses in these standard register locations and, in most cases, use them to produce a result that is left in standard location DD. 18