【導(dǎo)讀】IBMPC/AT硬體架構(gòu)與動(dòng)作原理。IBMPC/AT原版電路之功能方塊的內(nèi)容。主機(jī)板內(nèi)DATABus的流程。高/低位元組和系統(tǒng)緩衝器簡(jiǎn)圖

　　

【正文】 11 Reserved ASZ[1:0] Description 0 0 0= A[35:3] 4GB 0 1 4GB=A[35:3]64GB 1 x Reserved Table ASZ[1:0] Signal Decode 42 POWERGOOD Relationship at PowerOn VCCcore VCCL2 PWRGOOD RESET Clock 1 ms Ratio BCLK 43 Ratio of processor Core Frequency to System Bus Frequency LINT[1] LINT[0] IGNNE A20M Reserved H L H H 3/2 H H L H 2 H H H H 5/2 L H L L 3 L L H L 7/2 L H H L 4 L L L H 9/2 L H L H 5 L L H H 11/2 L H H H 6 H L L L 13/2 H H L L 7 H L H L 15/2 H H H L 8 H L L H System Bus To Core Frequency Multiplier Configuration 44 Processor PCI Local Bus Bridge/ Memory Controller Cache DRAM LAN SCSI Exp Bus Xface Base I/Os ISA/EISA – Micro Channel Audio Motion video Graphics 45 ADDRESS PHASE DATA PHASE DATA PHASE DATA PHASE BUS TRANSACTION Figure : Basic Read Operation 1 2 3 4 5 6 7 8 9 CLK FRAME AD ADDRESS DATA1 DATA2 DATA3 C/BE BUS CMD BE39。S IRDY WAIT DATA TRANSFER WAIT DATA TRANSFER WAIT DATA TRANSFER TRDY DEVSEL 46 Command Definition C/BE[3::0] Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate 47 DATA PHASE DATA PHASE DATA PHASE BUS TRANSACTION 1 2 3 4 5 6 7 8 9 CLK FRAME AD ADDRESS DATA1 DATA3 C/BE BUS CMD BE39。S3 IRDY WAIT DATA TRANSFER WAIT DATA TRANSFER WAIT DATA TRANSFER TRDY DEVSEL DATA2 BE39。S1 BE39。S2 ADDRESS PHASE Figure : Basic Write Operation 48 PCI COMPLIANT DEVICE AD[63::32] C/BE[7::4] AD[31::00] C/BE[3::0] PAR Address amp。 Data Interface Control FRAME IRDY TRDY STOP CLK SERR IDSEL PERP GNT REQ STOP RST Arbtration (masters only) Error Reporting System TDI TDO TCK TMS TRST 64Bit Extension Interface Control Interrupts JTAG (IEEE ) INTA INTB INTC INTD PAR64 REQ64 LOCK ACK64 Figure : PCI Pin List Required Pins Optional Pins 49 Compact PCI feature(part 1) 1. 33 and 66 MHz PCI performance 2. 32and 64bit data transfers 3. 8 CompactPCI slots per bus segment at 33 MHz 4. 5 CompactPCI slots per bus segment at 66 MHz 5. Industry standard software support 6. 3U small form factor(100 mm by 160 mm) 7. 6U form factor( mm by 160 mm) 50 Compact PCI Features(part 2) 8. IEEE( , and ) Eurocard packaging 9. Wide variety of available I/O 10. System Management Bus (CompactPCI Specification PICMG September 24,1999) 51 2 3 4 5 6 7 8 1 =SYSTEM SLOT =PERIPHERAL SLOT + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + + + + + + ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. ……. + + + + + Figure : 3U CompactPCI Backplane Example 7p2 2P2 22 1 25 22 1 25 z a b c d e f 2P1