51單片機(jī)簡介外文翻譯-單片機(jī)-資料下載頁
2025-01-19 06:35本頁面
【導(dǎo)讀】和128字節(jié)的存取數(shù)據(jù)存儲(chǔ)器，這種器件采用。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片。機(jī)能夠被應(yīng)用到控制領(lǐng)域中。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并。支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)。存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)。據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)TTL電路。當(dāng)“1”被寫入P0口時(shí)，每個(gè)管腳都能夠作為。據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。外部程序時(shí)，應(yīng)設(shè)置ALE無效。XTAL2分別是該放大器的輸入端和輸出端。保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。許中斷的事件被激活，IDL被硬件清除，即刻終止閑散工作模式。
【正文】 xternal clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Powerdown Mode In the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the powerdown mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. 12 When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
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