【導讀】和128字節(jié)的存取數(shù)據(jù)存儲器，這種器件采用ATMEL公。司的高密度、不容易丟失存儲技術生產(chǎn)，并且能夠與MCS-51系列的單片機兼容。性價比的應用場合，可靈活應用于各種控制領域。信口，片內(nèi)振蕩器及時鐘電路。同時，AT89C51可降至0Hz的靜態(tài)邏輯操作，并支持。串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工。作并禁止其它所有部件工作直到下一個硬件復位。AT89C51單片機是一個行業(yè)標準架構(gòu)，被廣泛接受和應用，并作為一種開發(fā)工具。醫(yī)學研究理事會和高級微電子研究所都選擇這個設備，但他們論證的是兩種。醫(yī)學研究理事會的實例是使用時間鎖存，需要具體時間以確保單。粒子效應減少到最低限度。藝的設計原則來實現(xiàn)其結(jié)果。據(jù)總線復用，在訪問期間即或內(nèi)部上拉電阻。腳會被微弱拉高，單片機執(zhí)行外部程序時，應設置ALE無效。編程完成后，變?yōu)楦唠娖奖硎緶蕚渚途w狀態(tài)。石晶振蕩和陶瓷振蕩均可采用。如采用外部時鐘源驅(qū)

　　

【正文】 oscillator to restart and stabilize. Programming the Flash: The AT89C51 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a highvoltage (12volt) or a lowvoltage (VCC) program enable signal. The lowvoltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled. The AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash memory, the entire memory must be erased using the chip erase mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals. 4. Raise EA/VPP to 12V for the highvoltage programming mode. 5. Pulse ALE/ PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than . Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Data polling may begin any time after a write cycle has been initiated. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The whole array and three lockbit PEROM electrical erase control signals through the right bination and maintain ALE pin is low 10ms to plete. Cleaning operation in the chip, code arrays were all written 1 and in any nonempty memory byte has been programmed to repeat the past, the operation must be executed. In addition, AT89C51 with steadystate logic, and can be in the low to zero frequency under the conditions of static logic, and supports two software selectable powerdown mode. In idle mode, CPU stop working. But the RAM, timers, counters, serial port and interrupt system are still working. In the powerdown mode, to save the contents of RAM and a freeze oscillator, to prohibit the use of other chip functions until the next until a hardware reset. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows: (030H) = 1EH indicates manufactured by ATMEL (031H) = 51H indicates AT89C51 singlechip (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface: Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to pletion. Watchdog (WDT) circuit: Watchdog (WDT) reset circuit is to achieve the main functionality. When the MCU is running an infinite loop occurs when the watchdog (WDT) can play a protection circuit to achieve reduction effect.