【導(dǎo)讀】VoltageParameters. Currentmodelogic(CML)buffer. Timingparameters. ACcoupling. 8B10Bencoding. path.class.singleendedsignal.moreground.signalwillbelost.disturbances.endedsignaling.beroutedtogether.routingchallenges.

　　

【正文】 e same as the running disparity found at the end of the 4 bit subblock (and the running disparity at the beginning of the next symbol / 6 bit subblock is the same as that found at the end of the this symbol) ? Again, a given subblock or symbol can have an actual disparity number of either a zero (neutral), +2 or –2, though the Running Disparity is only said to be Positive, Negative or Neutral. 60 12/4/2020 Differential Signaling 下載 8b/10b Running Disparity Calculation Algorithm: ? Assumptions: The 8b to 10b encoding has already been done。 A current disparity value is already assumed ? Process: Calculate the disparity for the leftmost 6 bits first, keeping in mind the current disparity value before entering the algorithm. Then calculate the disparity for the rightmost 4 bits keeping in mind the disparity value determined after analyzing the previous 6 bits. The disparity for both the 6bit and the 4bit blocks should be calculated as follows: 61 12/4/2020 Differential Signaling 下載 8b/10b Running Disparity Calculation Method ? Method: If of 1’s 0’s Disparity = Positive (1) Else if of 0’s 1’s Disparity = Negative (0) Else if 6bit = 000111 Then Disparity = Positive (1) Else if 6bit = 111000 Then Disparity = Negative (0) Else if 4bit = 0011 Then Disparity = Positive (1) Else if 4bit = 1100 Then Disparity = Negative (0) Else Disparity = Disparity (if none of the above, then the disparity value doesn’t change) Note: Assuming a encoding, more 1’s across the entire 10b code yields positive disparity, more 0’s yields negative disparity, and even ’s of 1’s and 0’s yields neutral disparity (. disparity is the same as it was before). 62 12/4/2020 Differential Signaling 下載 8b/10b Disparity amp。 Encoding Example: ? Transmitter keeps running track of current disparity (it is either RD, RD+ or neutral) Neutral means the disparity tracker keeps the previous RD or RD+ value ? A Running Disparity of RD+ is always followed by an RD encoding and vice versa If Running Disparity is RD+, the following is encoded for the data byte F1: HGF EDCBA ? abcdei fghj 111 10001 ? 100011 0111 (RD encoding) If Running Disparity is RD, the following is encoded for the data byte F1: HGF EDCBA ? abcdei fghj 111 10001 ? 100011 0001 (RD+ encoding) 63 12/4/2020 Differential Signaling 下載 8b/10b Disparity amp。 Encoding Example: ? Note that the number of ones and zeros in the currently chosen encoding works to balance out the offset in the number of ones and zeroes (tracked by the Running Disparity value) from the previous encoding . : Don’t confuse the definition of Positive Disparity with the RD+ encoding choice! Positive Disparity means there is a current running total of more ones than zeros! Thus, an RD+ encoding generally has more zeros than ones! ? Also note that it is possible that the 4bit subblock of a RD or RD+ symbol encoding can yield a negative or positive disparity, respectively thus forcing more than one RD encoding to be used consecutively… 64 12/4/2020 Differential Signaling 下載 Summary: Example conversion HEX Data Byte (8b) to be Encoded OR Binary Data Byte (8b) to be Encoded 10b Encoded symbol (RD) 10b Encoded symbol (RD+) F1 100011 0111 100011 0001 1111 0001 65 12/4/2020 Differential Signaling 下載 Possible Patterns… ? Repeating Comma [] Pattern (RD followed by RD+): 001111 1010 110000 0101 001111 1010 110000 0101 (RD) (RD+) (RD) (RD+) 6 bit encoding starts with an RD and uses an positive disparity encoding….6 bits encoding yields an RD+…..4bit encoding starts with a RD +…4bit encoding picks a negative (or neutral encoding) and thus yields a neutral and thus keeps the RD+. Checks out…. ? Low Frequency Pattern?? ( (RD followed by RD) 011110 0100 011110 0100 011110 0100 011110 0100 (RD) (RD) (RD) (RD) 100001 1011 100001 1011 100001 1011 100001 1011 (RD+) (RD+) (RD+) (RD+) 66 12/4/2020 Differential Signaling 下載 Possible Patterns… ? High transition density/frequency pattern: (RD followed by RD+) 101010 1010 101010 1010 101010 1010 101010 1010 (RD) (RD+) (RD) (RD+) ? Low transition density pattern: (RD) amp。 (RD+) (although is reserved....) 001111 1000 001111 1000 001100 1100 001111 1000 001100 1100 (RD) (RD+) (RD) (RD+) (RD) amp。 (RD+) 1100110110 0011000110 1100110110 0011000110 (RD) (RD+) (RD) (RD+) ? Composite pattern: (RD) amp。 (RD) 011110 0001 101100 1000 011110 0001 101100 1000 (RD) (RD) (RD) (RD) 67 12/4/2020 Differential Signaling 下載 References ? Infiniband Architecture Release Specification October 24, 2020, Volume 2, Section (beginning with page 66) ? Franaszek amp。 Widmer (IBM) Patent 4,486,739 December 4, 1984, Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code ? 3GIO Architecture Specification Key Developer Draft August 21, 2020, Appendix C, pg148154 ? ANSI , clause 11 (and also IEEE , ). 68 12/4/2020 Differential Signaling 下載 Other sources of mon mode ? A DC voltage will build up across the blocking capacitor if the charge and discharge is not equal. ? We have see this can happen if the number of bits is unbalance. ? Another source of imbalance is possible if the duty cycle of the one and zeros is not 50%. ? This can happen in two ways The time for a one differs from that of a zero. This can be caused by edge jitter. The rising time and falling time are miss matched On the next slide we will t