waferfabricationprocesstechnology(英文版)(編輯修改稿)
2025-03-09 00:52 本頁面
【文章內(nèi)容簡介】 ResistVia EtchRemove ResistFoxpolySi polySip+ p+Metal 1n+ n+BPTEOSsilicon substratepwell nwellCMOS Contacts InterconnectsDeposit Metal 2Metal 2Metal 2Deposit ResistUV ExposureDevelop ResistEtch Metal 2Remove ResistDeposit PassivationFoxpolySi polySip+ p+Metal 1n+ n+BPTEOSIMD1 SOGPassivation Process Cross sectionPad oxideP SubstrateOD SiN Process Cross sectionP Substrate Process Cross sectionP SubstratePwell maskPwellNAPTVTNB11 Pwell/NAPT/VTN ImplantNwell maskP31 Nwell/P_APT/VTP ImplantNwellPAPTVTP Process Cross sectionP SubstratePwellNAPTVTNNwellNfieldPAPTMask 132 HF Wet dip and Grow Gate oxide2 Process Cross sectionPoly NLDDP SubstrateNLDDPwellNAPTVTNNwellPAPTVTPPolyNLDD implantNLDD 114 mask PLDD 113 maskPLDD implant Process Cross sectionPoly PLDDPLDD NLDDP SubstrateNLDDPwellNAPTVTNNwellPAPTVTPPolyPLDD 197 mask ( )Ppocket/PLDD impNLDD 116 mask ()NLDD21 As/NLDD22P31 imp Process Cross sectionPoly P SubstratePwellNAPTNwellPAPTVTPPolyPSD NSD NSD NSDPSD PSDPSD 197 maskNSD 198 maskNSD imp Process Cross sectionPoly P SubstratePwellNAPTNwellP
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