【文章內(nèi)容簡(jiǎn)介】 nal logic circuitry of the AD574A.The control signals CE, CS, and R/C control the operation of the converter. The state of R/C when CE and CS are both asserted determines whether a data read (R/C = 1) or a convert (R/C = 0) is in progress. The register control inputs AO and 12/8 control conversion length and data format. The AO line is usually tied to the least significant bit of the address bus. If a conversion is started with AO low, a full 12bit conversion cycleis initiated. If AO is high during a convert start, a shorter 8bit conversion cycle results. During data read operations, AO determines whether the threestate buffers containing the 8 MSBs of the conversion result (AO = 0) or the 4 LSBs (AO = 1) are enabled. The 12/8 pin determines whether the output data is to be organized as two 8bit words (12/8 tied to DIGITAL COMMON) or a single 12bit word (12/8 tied to VLOGIC). The 12/8 pin is not TTLpatible and must be hardwired to either VLOGIC or DIGITAL COMMON. In the 8bit mode, the byte addressed when AO is high contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to 8bit buses without the need for external threestate buffers. It is not remended that AO change state during a data read operation. Asymmetrical enable and disable times of the threestate buffers could cause internal bus contention resulting in potential damage to the AD574A.Figure 6. AD574A Control LogicAn output signal, STS, indicates the status of the converter. STS goes high at the beginning of a conversion and returns low when the conversion cycle is plete.TIMINGThe AD574A is easily interfaced to a wide variety of microprocessors and other digital systems. The following discussion of the timing requirements of the AD574A control signals should provide the system designer with useful insight into the operation of the device.Figure 7 shows a plete timing diagram for the AD574A convert start operation. R/C should be low before both CE and CS are asserted。 if R/C is high, a read operation will momentarily occur, possibly resulting in system bus contention. Either CE or CS may be used to initiate a conversion。 however, use of CE is remended since it includes one less propagation delay than CS and is the faster input. In Figure 7, CE is used to initiate the conversion.Figure 7Once a conversion is started and the STS line goes high, convert start mands will be ignored until the conversion cycle is plete. The output data buffers cannot be enabled during conversion.Figure 8 shows the timing for data read operations. During data read operations, access time is measured from the point where CE and R/C both are high (assuming CS is already low). If CS is used to enable the device, access time is extended by 100 ns.Figure 8. Read Cycle TimingIn the 8bit bus interface mode (12/8 input wired to DIGITAL COMMON), the address bit, AO, must be stable at least 150 ns prior to CE going high and must remain stable during the entire read cycle. If AO is allowed to change, damage to the AD574A output buffers may result.“STANDALONE” OPERATIONThe AD574A can be used in a “standalone” mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. In this mode, CE and 12/8 are wired high, CS and AO are wired low, and conversion is controlled by R/C. The threestate buffers are enabled when R/C is high and a conversion starts when R/C goes low. This allows two possible control signals—a high pulse or a low pulse. Operation with a low pulse is shown in Figure 11. In this case, the outputs are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is pleted. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid.Figure 11. Low Pulse for R/C—Outputs Enabled After ConversionIf conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to threestate (and remain threestate) until