【文章內(nèi)容簡(jiǎn)介】 processor control. How would I use a DDS device for FSK encoding? Binary frequencyshift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the markspace data and the transmitted signal.Figure 7. A DDSbased FSK encoder.Figure 6. FSK modulation.This encoding scheme is easily implemented using a DDS. The DDS frequency tuning word, representing the output frequencies, is set to the appropriate values to generate f0 and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the two required tuning words into the device before transmission. In the case of the AD9834, two frequency registers are available to facilitate convenient FSK encoding. A dedicated pin on the device (FSELECT) accepts the modulating signal and selects the appropriate tuning word (or frequency register). The block diagram in Figure 7 demonstrates a simple implementation of FSK encoding.And how about PSK coding? Phaseshift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant and the phase of the transmitted signal is varied to convey the information. Of the schemes to acplish PSK, the simplestknown as binary PSK (BPSK)—uses just two signal phases, 0 degrees and 180 degrees. BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift for a logic 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave reverses (changes by 180 degrees), then the signal state changes (from low to high, or from high to low). PSK encoding is easily implemented with DDS ICs. Most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, thus generating a PSK output signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase registers to be selected using a dedicated toggling input pin (PSELECT), which alternates between the registers and modulates the carrier as required. More sophisticated forms of PSK employ four or eight wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In fourphase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, –90, and 180 degrees。 each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow plex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers. Can multiple DDS devices be synchronized for, say, IQ capability? Figure 8. Multiple DDS ICs insynchronous mode.It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do IQ modulation.A reset must be asserted after powerup and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the mon reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phaseoffset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of degree. [For further details on synchronizing multiple DDS units please see Application Note AN605.] What are the key performance specs of a DDS based system?Phase noise, jitter, and spuriousfree dynamic range (SFDR).Phase noise is a measure (dBc/Hz) of the shortterm frequency instability of the oscillator. It is measured as the singlesideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry.Do DDS devices have good phase noise?Figure 9. Typical output phase noise plotfor the AD9834. Output frequency is 2MHz and M clock is 50 MHz.Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system。 and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binarycoded word, there is no truncation error. For ratios requiring more bits than are avai