【正文】 MCLK的是設(shè)置為25MHz和所需的輸出頻率設(shè)置為10MHz。一個(gè)例子是如圖11所示。即使是一個(gè)簡單的放大器，逆變器，或?qū)⒂兄诰彌_抖動(dòng)信號(hào)。它是衡量作為單邊帶從頻率變化造成的噪音低于在使用振蕩器的（工作頻率為1Hz）的帶寬在兩個(gè)或多個(gè)頻率位移振蕩器工作頻率振幅分貝。改變這種調(diào)制的載波相位，因此產(chǎn)生的PSK輸出信號(hào)。圖6顯示了一個(gè)例子，空間數(shù)據(jù)和傳輸信號(hào)之間的關(guān)系。圖5 流過DDS的信號(hào)然而，對于實(shí)際應(yīng)用中，輸出頻率是有限的，在一定程度改善波形質(zhì)量的重建，并允許濾波輸出。每個(gè)階段輪指向?qū)?yīng)的等效點(diǎn)1波周期的正弦。圖2顯示了方波、三角波和正弦波輸出。 it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and pletes its equivalent of a sinewave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 referenceclock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 referenceclock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:where: fOUT = output frequency of the DDS M = binary tuning word fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bits Changes to the value of M result in immediate and phasecontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phaselocked loop. As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave? Figure 5. Signal flow through the DDS architecture.A phase to amplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)—with unneeded lesssignificant bits eliminated by truncation—into the sinewave amplitude information that is presented to the (10 bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a plete sine wave from onequartercycle of data from the phase accumulator. The phaseto amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5.What are popular uses for DDS? Applications currently using DDSbased waveform generation fall into two principal categories: Designers of munications systems requiring agile (., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its bination of spectral performance and frequencytuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission. Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external ponents that would normally need to be changed when using traditional analogprogrammed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or pensate for temperature drift. Suchapplications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedancebased sensor), to generate pulsewave modulated signals for microactuation, or to examine attenuation in LANs or telephone cables. What do you consider to be the key advantages of DDS to designers of realworld equipment and systems? Today’s cost petitive, high performance, functionally integrated DDS ICs are being mon in both munication systems and sensor applications. The advantages that make them attractive to design engineers include: ? digitally controlled microhertz frequencytuning and subdegree phasetuning capability, ? extremely fast hopping speed in tuning output frequency (or phase)。DDS器件現(xiàn)已可以產(chǎn)生從1到400MHz的頻率，（時(shí)鐘基于103MHz兆赫）。它是如何工作的？連續(xù)時(shí)間正弦信號(hào)的角度范圍內(nèi)有一個(gè)重復(fù)的階段0至2。無回路的建立時(shí)間發(fā)生在一個(gè)循環(huán)鎖相內(nèi)。我會(huì)用怎樣的FSK編碼DDS設(shè)備？二進(jìn)制頻移鍵控（簡稱為FSK）是一個(gè)最簡單的數(shù)據(jù)編碼形式。容易實(shí)現(xiàn)的PSK編碼是用DDS芯片。多個(gè)DDS的同步如需進(jìn)一步詳情請參閱應(yīng)用筆記AN605。這當(dāng)然是不可能的，因?yàn)榧词故亲詈玫恼袷幤饕矔?huì)由于噪音和其他來源的實(shí)際組件構(gòu)建不完善。較低的頻率設(shè)定在（b）有更多的點(diǎn)，形狀的波形（但不夠的，一個(gè)真正干凈的波形），并給出了一個(gè)更為現(xiàn)實(shí)的圖片，在二次諧波頻率，大約是50dB以下信號(hào)（SFDR=50dB）。由專用軟件攜帶，用戶可以測試/評估。對于最好的無雜散動(dòng)態(tài)范圍，必須首先具有高品質(zhì)的振蕩器。他們的大小和分布取決于選擇的代碼字。在圖8里，兩個(gè)AD9834s是用一個(gè)程序參考時(shí)鐘引腳，以同樣的重置用于更新兩個(gè)部分。頻移鍵控PSK編碼怎么樣？相移鍵控（PSK）是另一種數(shù)據(jù)編碼的簡單形式。另外，許多工業(yè)和生物醫(yī)學(xué)應(yīng)用DDS的波形發(fā)生器作為一個(gè)可編程的器件。這個(gè)字形成相位步長之間的參考，它有效地設(shè)置跳過多少分左右相輪。反過來，DAC把這個(gè)數(shù)字轉(zhuǎn)換為相應(yīng)值的模擬電壓或電流。為什么要使用直接數(shù)字頻率合成器（DDS）？不同頻率和配置文件是不是有其他的方法能夠很容易地產(chǎn)生頻率？能夠準(zhǔn)確地產(chǎn)生和控制波形已經(jīng)成為一些行業(yè)的主要要求。由于設(shè)計(jì)方面和工藝技術(shù)的進(jìn)步，今天的DDS器件是非常緊湊的小功率。在使用正弦查找表時(shí)，用相位累加器計(jì)算一個(gè)階段（角）的地址查找表，輸出幅度的數(shù)字值對應(yīng)相位角的正弦。遞增幅度取決于輸入字（米）。這些應(yīng)用包括使用DDS調(diào)制，作為一個(gè)PLL參考頻率，以提高整體可調(diào)，作為本地振蕩器，甚至直接射頻傳輸。該框圖圖7演示了簡單的FSK信號(hào)的編碼。多個(gè)DDS器件可以同步嗎，也就是說，智商能力？圖8 多個(gè)DDS同步模式它可以使在同一主機(jī)兩個(gè)單DDS器件的時(shí)鐘運(yùn)行輸出的兩個(gè)信