【正文】 這些工具將如何幫助我的DDS方案？所有這一切需要的是必要的頻率輸出和系統(tǒng)的參考時(shí)鐘頻率。由于每個(gè)時(shí)鐘將已經(jīng)有一定抖動(dòng)，選擇一個(gè)低抖動(dòng)振蕩器是至關(guān)重要的開始。DDS器件具有良好的相位噪音？對采樣系統(tǒng)的噪聲，取決于很多因素。更多復(fù)雜的PSK形式選用4或8波階段。DDS的頻率控制字，代表輸出頻率，設(shè)置為適當(dāng)?shù)闹祦砩蒮0和f1的，因?yàn)樗鼈冊?和1以進(jìn)行傳輸。試問，線性輸出波形怎樣轉(zhuǎn)化為正弦波？A相方法振幅查找表用于轉(zhuǎn)換相位累加器的瞬時(shí)輸出值（28比特AD9833）將正弦波振幅信息，提交（10位）到D/A轉(zhuǎn)換器。一個(gè)車輪周圍的相速度向量，為一個(gè)常數(shù)，正弦波輸出結(jié)果為一個(gè)完整周期。這些模塊的代表圖如圖3。 each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow plex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers. Can multiple DDS devices be synchronized for, say, IQ capability? Figure 8. Multiple DDS ICs insynchronous mode.It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do IQ modulation.A reset must be asserted after powerup and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the mon reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phaseoffset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of degree. [For further details on synchronizing multiple DDS units please see Application Note AN605.] What are the key performance specs of a DDS based system?Phase noise, jitter, and spuriousfree dynamic range (SFDR).Phase noise is a measure (dBc/Hz) of the shortterm frequency instability of the oscillator. It is measured as the singlesideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry.Do DDS devices have good phase noise?Figure 9. Typical output phase noise plotfor the AD9834. Output frequency is 2MHz and M clock is 50 MHz.Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system。例如AD9833，一個(gè)基于DDS的可編程波形發(fā)生器（圖1），消耗的最大功率為30mW。完整的DDS是什么意思？D/A轉(zhuǎn)換器和一個(gè)DDS的單一芯片的整合通常被稱為一個(gè)完整的DDS的解決方案，ADI公司的普通性質(zhì)DDS。如果M值更改為0111 ... 1111，相位累加器溢出后，將只有2參考時(shí)鐘周期（取決于奈奎斯特最低要求）。你認(rèn)為對于現(xiàn)實(shí)世界系統(tǒng)設(shè)備的設(shè)計(jì)者，DDS的關(guān)鍵優(yōu)點(diǎn)是什么？今天的成本競爭力，高性能，功能集成DDS IC是越來越常見的兩種通信系統(tǒng)和傳感器應(yīng)用。如果波階段的不改變，信號狀態(tài)保持不變（低或高）。當(dāng)新的數(shù)據(jù)同時(shí)發(fā)送到多個(gè)DDS的單位，一連貫的相位關(guān)系可以保持，以及它們的相對相位偏移可預(yù)見由相位偏移寄存器方式轉(zhuǎn)變。怎么樣抖動(dòng)？度均方根抖動(dòng)是數(shù)字信號的動(dòng)態(tài)位移的長期測量。輸出頻率正好是1/3的主時(shí)鐘頻率（MCLK）。如果發(fā)射機(jī)的輸出發(fā)送到其他頻段的雜散信號，他們可能會損壞鄰近信號或中斷信號。DAC的量化或線性誤差會造成噪音及諧波。傳輸任何數(shù)據(jù)之前，先復(fù)位該DDS，做之前必須斷電。在這計(jì)劃完成的PSK，（最簡單的）被稱為二進(jìn)制的PSK（BPSK調(diào)制），只用兩個(gè)信號相位，0度和180度。DDS調(diào)整簡單，找到共振的頻率或補(bǔ)償溫度漂移。該輪在數(shù)字離散相點(diǎn)中，取決于分辨率的相位累加器（n），這決定了DDS的調(diào)諧。如果相位增量大，相位累加器會迅速通過正弦查找表，從而產(chǎn)生高頻率的正弦波。圖1 AD9833波形發(fā)生器設(shè)計(jì)師以相位鎖定回路（PLL）為基礎(chǔ)的需要非常高的頻率的合成技術(shù)，以DAC的動(dòng)態(tài)規(guī)劃的數(shù)字toanalog轉(zhuǎn)換器（輸出產(chǎn)生較低的頻率任意波形）來產(chǎn)生許多可能產(chǎn)生的頻率，但DDS技術(shù)迅速獲得了解決頻率（或波形）產(chǎn)生和工業(yè)應(yīng)用要求的方法，因?yàn)閱涡酒呻娐菲骷梢援a(chǎn)生簡單的可編程的模擬輸出高分辨率和準(zhǔn)確性的波形。 the largest spur, at the secondharmonic frequency, is about 50 dB below the signal (SFDR = 50 dB).(a) fOUT = (b) fOUT = .Figure 10. Output of an AD9834 with a 50MHz master clockFigure 11. Screen presentation provided by an interactive design tool.A sinx/x presentation of a typical device output.Do you have tools that make it easier to program and predict the performance of the DDS?The online interactive design tool is an assistant for selecting tuning words, given a reference clock and desired output frequencies and/or phases. The required frequency is chosen, and idealized output harmonics are shown after an external reconstruction filter has been applied. An example is shown in Figure 11. Tabular data is also provided for the major images and harmonics.How will these tools help me program the DDS?Figure 12. Typical display of programming sequence.All that’s needed is the required frequency output and the system’s reference clock frequency. The design tool will output the full programming sequence required to program the part. In the example in Figure 12, the MCLK is set to 25 MHz and the desired output frequency is set to 10MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register.How can I evaluate your DDS devices?All DDS devices have an evaluation board available for purchase. They e with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note acpanying each evaluation board contains schematic information and shows best remended boarddesign and layout practice.外文翻譯（譯文）關(guān)于直接數(shù)字頻率合成器由伊娃墨菲[ ]寇斯拉特里[ ]什么是直接數(shù)字頻率合成器？直接數(shù)字頻率合成器（DDS）是一種通過產(chǎn)生一個(gè)以數(shù)字形式時(shí)變的信號，然后執(zhí)行由數(shù)字至模擬轉(zhuǎn)換的方法。它的頻率取決于兩個(gè)變量，參考時(shí)鐘頻率和（控制字）數(shù)字編程的頻率。相位累加器對應(yīng)于點(diǎn)的波周期輸出的正弦。該相位對振幅查找表其余數(shù)據(jù)通過閱讀然后再向前，這形象地顯示在圖5。在AD9834，兩個(gè)頻率寄存器，可方便的進(jìn)行FSK編碼。在fourphase調(diào)制（正交PSK或QPSK調(diào)制），可能相角為0，+90，90，和180度，每相移可以代表兩個(gè)信號分子。對于一個(gè)完全可以由一個(gè)二進(jìn)制編碼表示的比例，也沒有截?cái)嗾`差。隨著頻率的劃分，相同數(shù)量的抖動(dòng)一段較長的時(shí)間內(nèi)發(fā)生，減少其對系統(tǒng)時(shí)間的百分比。以圖12為例，