單片機畢業(yè)設計外文翻譯單片機at89c(編輯修改稿)
2024-09-03 00:52 本頁面
【文章內(nèi)容簡介】 programming, for parts that require 12volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPowerdown ModeIn the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the powerdown mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random
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鄂ICP備17016276號-1