外文文獻(xiàn)翻譯中英文對(duì)照自動(dòng)化相關(guān)可編程邏輯控件(編輯修改稿)
2025-09-02 19:38 本頁(yè)面
【文章內(nèi)容簡(jiǎn)介】 y (Library). Among them, the entity is the basic unit of a VHDL program, by entity and the structure of two parts: the physical design system that is used to describe the external interface signal。 structure used to describe the behavior of the system, the system processes or system data structure form. Configuration select the required language from the library system design unit to form different versions of different specifications, so that the function is designed to change the system. Collection of records of the design module package to share the data types, constants, subroutines and so on. Database used to store the piled entities, the body structure, including the collection and configuration: one is the development of engineering software user, the other is the manufacturer39。s database. VHDL, the main features are: ① powerful, high flexibility: VHDL language is a powerful language structure, clear and concise code can be used to design plex control logic. VHDL language also supports hierarchical design, support design databases and build reusable ponents. Currently, VHDL language has bee a design, simulation, synthesis of standard hardware description language. ② Device independence: VHDL language allows designers to generate a design do not need to first select a specific device. For the same design description, you can use a variety of different device structures to achieve its function. So the design description stage, able to focus on design ideas. When the design, simulation, after the adoption of a specific device specified integrated, adapter can be. ③ Portability: VHDL language is a standard language, so the use of VHDL design can be carried out by different EDA tool support. Transplanted from one to another simulation tools, synthesis tools from a port to another integrated tool, from a working platform into another working platform. EDA tools used in a technical skills, in other tools can also be used. ④ topdown design methods: the traditional design approach is bottomup design or flat design. Bottomup design methodology is to start the bottom of the module design, the gradual formation of the functional modules of plex circuits. Advantage of this design is obvious because it is a hierarchical circuit design, the general circuit submodule are in accordance with the structure or function of division, so the circuit level clear, clear structure, easy people to develop, while the design archive file is easy, easy munication. Bottomup design is also very obvious shortings, the overall design concept is often not leaving because the cost of months of lowlevel design in vain. Flat design is a module containing only the circuit, the circuit design is straightforward and, with no division structure and function, it is not hierarchical circuit design. Advantages of small circuit design can save time and effort, but with the increasing plexity of the circuit, this design highlights the shortings of the abnormal changes. Topdown design approach is to design toplevel circuit description (top m
研究報(bào)告相關(guān)推薦
鄂ICP備17016276號(hào)-1