外文資料翻譯譯文(編輯修改稿)
2024-12-08 08:05 本頁面
【文章內(nèi)容簡介】 unters, a five vector twolevel interrupt architecture,a full duplex serial port, onchip oscillator and clock addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePowerdown Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset. Pin Configurations Block Diagram Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8bit opendrain bidirectional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs. Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups. Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification. Port 1 Port 1 is an 8bit bidirectional I/O port with internal Port 1 output buffers can sink/source four TTL 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal 1 also receives the loworder address bytes during Flash programming and verification. Port 2 Port 2 is an 8bit bidirectional I/O port with internal Port 2 output buffers can sink/source four TTL 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8bit bidirectional I/O port with internal Port 3 output buffers can sink/source four TTL 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN P
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