操作系統(tǒng)精髓與設(shè)計原理英漢對照6th(編輯修改稿)
2025-02-04 14:54 本頁面
【文章內(nèi)容簡介】 must pause to wait for device Common Classes of Interrupts中斷的通常等級 Flow of Control without Interrupts無中斷控制流程 Interrupts and the Instruction Cycle終端和指令周期 Transfer of Control via Interrupts通過中斷的控制轉(zhuǎn)移 Instruction Cycle with Interrupts有中斷的指令周期 Short I/O Wait短 I/O等待 Long I/O wait長 I/O等待 Simple Interrupt Processing簡單的中斷處理 Changes in Memory and Registers for an Interrupt內(nèi)存和寄存器因中斷而產(chǎn)生的變化 Multiple Interrupts多中斷 ? Suppose an interrupt occurs while another interrupt is being 斷正在處理，另一個中斷出現(xiàn) – . printing data being received via munications line. ? Two approaches:兩個方法 – Disable interrupts during interrupt processing在一個中斷處理中禁止其他中斷 – Use a priority Sequential Interrupt Processing順序中斷處理 Nested Interrupt Processing嵌套中斷處理 Example of Nested Interrupts嵌套中斷的例子 Multiprogramming多道程序設(shè)計 ? Processor has more than one program to execute處理器有多個程序要執(zhí)行 ? The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O程序的執(zhí)行順序取決于他們的相對優(yōu)先級以及是否正在等待 I/O ? After an interrupt handler pletes, control may not return to the program that was executing at the time of the interrupt一個中斷處理完成后，控制權(quán)可能不會立刻返回到中斷時執(zhí)行到的程序（而可能轉(zhuǎn)移到其他待運行的具有更高優(yōu)先級的其他程序） Roadmap – Basic Elements – Processor Registers – Instruction Execution – Interrupts –The Memory Hierarchy – Cache Memory – I/O Communication Techniques Memory Hierarchy存儲器層次 ? Major constraints in memory存儲器的主要局限 – Amount容量 – Speed速度 – Expense費用 ? Faster access time, greater cost per bit存取時間越短，每位價格越高 ? Greater capacity, smaller cost per bit容量越大，每位價格越低 ? Greater capacity, slower access speed容量越大，存取速度越小 The Memory Hierarchy ? Going down the hierarchy沿著結(jié)構(gòu)向下 – Decreasing cost per bit每位價格遞減 – Increasing capacity容量遞增 – Increasing access time存取時間遞增 – Decreasing frequency of access to the memory by the processor存儲器訪問頻度遞減 Secondary Memory二級存儲器 ? Auxiliary memory（亦）輔助存儲器 ? External外部的 ? Nonvolatile非易失的 ? Used to store program and data files用于存儲程序和數(shù)據(jù)文件 Roadmap – Basic Elements – Processor Registers – Instruction Execution – Interrupts – The Memory Hierarchy –Cache Memory – I/O Communication Techniques Cache Memory高速緩存 ? Invisible to the OS對于操作系統(tǒng)不可見 – Interacts with other memory management hardware與其他存儲器管理硬件互動 ? Pr
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