計(jì)算機(jī)控制外文翻譯-其他專業(yè)(編輯修改稿)
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【文章內(nèi)容簡介】 to 0.N zeros are also shifted in from the left to fill vacated bit result of the shift instruction can be scanned at output CC0 bit and the OV bit are set to 0 by SHR_W if N is not equal to result of the shift instruction can be scanned at output OUT. The CC0 bit and the OV bit are set to 0 by SHR_W if N is not equal to 0. ENO has the same signal state as EN. Example E NI NNO U TE N OS H R _ WI 0 . 0M W 0M W 2M W 4( S )Q 4 . 0 The SHR_W box is activated by logic 1 at is loaded and shifted right by the number of bits specified with result is written to MW4. is set. SHL_DW Shift Left Double Word Symbol E NINNO U TE N OSH L _D W Paramete Data Type Memory Area Description EN BOOL I、 Q、 M、 L、 D Enable input ENO BOOL I、 Q、 M、 L、 D Enable output IN DWORD I、 Q、 M、 L、 D Value to shift N WORD I、 Q、 M、 L、 D Number of bit positions to shift OUT DWORD I、 Q、 M、 L、 D Result double word of shift Instruction Description SHL_DW (Shift Left Double Word) is activated by a logic 1 at the Enable (EN) Input. 蘭州交通大學(xué)畢業(yè)設(shè)計(jì)（論文） 6 The SHL_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the input N specifies the number of bits by which to N is larger than 32,the mand writes a 0 at output OUT and sets the bits CC0 and OV in the status word to 0.N zeros are also shifted in from the right to fill vacated bit result double word of the shift instruction can be scanned at output CC0 bit and the OV bit are set to 0 by SHL_DW if N is not equal to 0. ENO has the same signal state as EN. Example E NI NNO U TE N OS H L _ D WI 0 . 0M D 0M W 4M D 1 0( S )Q 4 . 0 The SHL_DW box is activated by logic 1 at is loaded and shifted left by the number of bits specified with result is written to is set. SHR_DW Shift Right Double Word Symbol E NINNO U TE N OSH R _D W Paramete Data Type Memory Area Description EN BOOL I、 Q、 M、 L、 D Enable input ENO BOOL I、 Q、 M、 L、 D Enable output IN DWORD I、 Q、 M、 L、 D Value to shift N WORD I、 Q、 M、 L、 D Number of bit positions to shift OUT DWORD I、 Q、 M、 L、 D Result double word of shift Instruction Description SHR_DW (Shift Right Double Word) is activated by a logic 1 at the Enable (EN) SHR_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the input N specifies the number of bits by which to N is larger than 32, the mand writes a 0 at output OUT and sets the bits CC0 and OV in the status word to 0. 蘭州交通大學(xué)畢業(yè)設(shè)計(jì)（論文） 7 The result double word of the shift instruction can be scanned at output OUT. ENO has the same signal state as EN. I NNO U T1 0 1 10 1 0 11 0 1 00 1 0 11 1 1 01 1 1 10 0 0 11 1 11 1 1 11 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 11 0 1 0 1 1 1 1T h e v a c a t e d p l a c e s a r e f i l
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