【正文】 arator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digitaltoanalog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D mand (input) to the counter while the upper trace is a hypothetical frequency modulating waveform. It is obvious that the term hypothetical is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is 177。s output acting as the Frequency Setting Word (FSW) instructs the DDS to produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associated stages up to the instrument39。 If n the phase step is equal to one, the accumulator will count by ones, taking 2 clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator counting by twos, taking 2n?1 clock cycles to plete one n?1 cycle of the output sinewave. It can easily be shown that for any integer m, where m 2 , the number of clock cycles taken to generate one cycle of the output sine wave is 2n /m, and the output frequency (fDDS) and the frequency resolution (fres) are given by the following formulas： m fclk 2n n fres= fclk/ 2 fDDS= For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n ) bees finer . it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output frequency that limits the counter39。FC 接受了 DDS 的 硬限幅波形以及未知的頻率。在 后一種情況下，代替頻率的周期只是估計(jì)的。一個(gè)已知（控制）的頻率波形在電路中產(chǎn)生，并反饋到強(qiáng)制它來(lái)接近未知 的（輸入）的頻率的頻率比較階段。過(guò)濾器使 數(shù)字化的正弦波更平穩(wěn)，生產(chǎn)連續(xù)輸出信號(hào)。如 果 n 是增加至 48 個(gè)具有相同的時(shí)鐘頻率，分辨率為 120 nHz 是可能的。 DDS 的時(shí)鐘頻率是非常重要的，因?yàn)樗鼫p小， 該方法的決議（定義為 fclk /）更出色，即它變得更精細(xì)的改進(jìn)。此外，該步驟將頻率 近似等于 DDS 的最大頻率的 1/ 4。該實(shí)現(xiàn)是基于一種改進(jìn)的相位 /頻率比 較器，由飛利浦在 74HC4046 PLL 設(shè)備中生產(chǎn)。 乍一看人們可以認(rèn)為，合成頻率可達(dá)到實(shí)測(cè)（鰭） ，然后計(jì)數(shù)器停止運(yùn)作。 如果我們考慮到案件的 DDS 的頻率等于未知之一，我們會(huì)發(fā)現(xiàn)，比較器的輸 出 將切換，說(shuō)明或者是 DDS 的頻率高于或低于下限未知。 如前所述，這個(gè)計(jì)數(shù)器的輸出被認(rèn)為是從 FSW 到 DDS 的階段。三角波形是 FSW 施加到 DDS 的模擬表示法。三角波形的坡度大小對(duì)于常數(shù)輸入頻率是 恒定并且取決于 U/ D 轉(zhuǎn)換計(jì)數(shù)器（水平軸）時(shí)鐘和 DAC（垂直軸）的電壓基準(zhǔn)。 這些設(shè)備和由高通 Q2240I 3S1 所生產(chǎn) DDS 相互聯(lián)系。 該微控制器還控制著整 個(gè)運(yùn)作的原型。與常規(guī)方法的比較已經(jīng)給出，兩個(gè)原型已建成并在實(shí) 驗(yàn)室測(cè)試。