【正文】 48, with the same clock frequency, a resolution of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n ) bees finer . it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output frequency that limits the counter39。s output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage parator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, as will be explained later. Although an analog implementation of the frequency parator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog ponents, wide frequency range of operation and shorter response time. Interaction between frequency parator and digital synthesizer After the successive approximation of the unknown frequency the Frequency Comparator realizes that the synthesized frequency is higher (lower) than the unknown one and produces a logic 0 (1) at the output which mands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be realized by the frequency parator and the synthesized frequency will keep on increasing for some clock cycles, until the parator detects the correct relation of it39。FC 接受了 DDS 的 硬限幅波形以及未知的頻率。優(yōu)勢(shì)是從 DDS 固有的高分辨率和環(huán)路 噪聲免疫力而來(lái)，從而設(shè)計(jì)同樣精確和不受影響的頻率計(jì)。在 后一種情況下，代替頻率的周期只是估計(jì)的。其他 [46]的 內(nèi)容是關(guān)于微處理器或以微控制器為基礎(chǔ)的。一個(gè)已知（控制）的頻率波形在電路中產(chǎn)生，并反饋到強(qiáng)制它來(lái)接近未知 的（輸入）的頻率的頻率比較階段。一個(gè)典型 的頻率設(shè)置字是 32 位寬，但 48 位合成器在較高的頻率分辨率也可使用。過(guò)濾器使 數(shù)字化的正弦波更平穩(wěn)，生產(chǎn)連續(xù)輸出信號(hào)。如果相位步等于 1，將累 加器的計(jì)數(shù)加 1，以時(shí)鐘周期，以滿(mǎn)足整個(gè) LUT 和生成一個(gè)周期的輸出正弦波。如 果 n 是增加至 48 個(gè)具有相同的時(shí)鐘頻率，分辨率為 120 nHz 是可能的。根據(jù)這一點(diǎn)， 接受的最大合成頻率為時(shí)鐘頻率的 25％（遠(yuǎn)低于奈奎斯特限制） 我們的原型使用一個(gè) 33 MHz 的時(shí)鐘將有效地?cái)?shù)到 8 兆赫。 DDS 的時(shí)鐘頻率是非常重要的，因?yàn)樗鼫p小， 該方法的決議（定義為 fclk /）更出色，即它變得更精細(xì)的改進(jìn)。為了克服特定頻率比較器的一些缺點(diǎn)校正階段已 被納入。此外，該步驟將頻率 近似等于 DDS 的最大頻率的 1/ 4。 在適當(dāng)?shù)男拚徒獯a后，數(shù)碼的 FSW 被顯示在在一個(gè)輸出設(shè)備中，即一臺(tái)液晶 顯示器或任何其他合適的方式。該實(shí)現(xiàn)是基于一種改進(jìn)的相位 /頻率比 較器，由飛利浦在 74HC4046 PLL 設(shè)備中生產(chǎn)。鑒于上述情況，電路操作如下：當(dāng)?shù)谝粋€(gè) 計(jì)數(shù)器（＃ 1）在一個(gè)時(shí)期內(nèi)遇到 DDS 的兩個(gè)未知頻率的上升邊緣，它設(shè)置 RS 觸發(fā)器的輸出。 乍一看人們可以認(rèn)為，合成頻率可達(dá)到實(shí)測(cè)（鰭） ，然后計(jì)數(shù)器停止運(yùn)作。我們將把這個(gè)時(shí)間稱(chēng)為 “遲滯 ” 。 如果我們考慮到案件的 DDS 的頻率等于未知之一，我們會(huì)發(fā)現(xiàn)，比較器的輸 出 將切換，說(shuō)明或者是 DDS 的頻率高于或低于下限未知。滯后的時(shí)間是 可變的。 如前所述，這個(gè)計(jì)數(shù)器的輸出被認(rèn)為是從 FSW 到 DDS 的階段。這是因?yàn)榍懊嫣岬降臏笞饔谩Ｈ遣ㄐ问? FSW 施加到 DDS 的模擬表示法。這款 DAC 不會(huì)顯示在電路的框圖 中。三角波形的坡度大小對(duì)于常數(shù)輸入頻率是 恒定并且取決于 U/ D 轉(zhuǎn)換計(jì)數(shù)器（水平軸）時(shí)鐘和 DAC（垂直軸）的電壓基準(zhǔn)。 第一種方法是一個(gè)低頻率的工具 （工 作達(dá) 15 千赫） 。 這些設(shè)備和由高通 Q2240I 3S1 所生產(chǎn) DDS 相互聯(lián)系。 由于 DAC 工作，生成的正弦波具有較高的諧波。 該微控制器還控制著整 個(gè)運(yùn)作的原型。 4 結(jié)論 在該文件中頻率測(cè)量的替代方法已經(jīng)提出。與常規(guī)方法的比較已經(jīng)給出，兩個(gè)原型已建成并在實(shí) 驗(yàn)室測(cè)試。 另一個(gè)重要優(yōu)勢(shì)是該系統(tǒng)的抗噪聲能力，由于其閉環(huán)的性質(zhì)。