【正文】 讀。根據(jù)比較器輸出的頻率，在每一個近似值中 頻率被分成兩個并且增加或減少到 DDS 的 FSW 中。這一階段也可用于測量提取，以顯示正確的讀數(shù)。時鐘頻率下降 的影響是其最大輸出頻率， 限制計數(shù)器的最大計數(shù)隨之降低。在砷化鎵產(chǎn)品來看， 我們可以看到，最近的 DDS 設(shè)計可以在高達(dá) 400 兆赫的時鐘頻率范圍運作 。 3 被提議的頻率測量技術(shù) 產(chǎn)生我們目前的設(shè)計的想法來自 DDS 的頻率分辨率極高的設(shè)備并且由它的 封閉循環(huán)的形式抗干擾執(zhí)行。 這是該系統(tǒng)能生成的最低的頻率， 也是它的頻率分辨率。在凡方波輸出需要的應(yīng)用中，這由 一個硬限制器在經(jīng)過過濾器之后得到。一個 相位累加器產(chǎn)生連續(xù)的正弦查找表的地址，并生成一個數(shù)字正弦波輸出。產(chǎn)生上述提及的受控的頻率波形是一個直接 數(shù)字合成器。 上述方法的特點是開環(huán)方法，即數(shù)字計數(shù)器來計數(shù)在預(yù)定 tinle 間隔，之后計算 結(jié)果。本文獻的第 [1]部分的某些文件處 理了低頻率的測量問題并集中在心臟（心臟）信號的頻率范圍（幾赫茲）或在電 源頻率（ 5060 赫茲） 。所有額外相關(guān)的階段 都被儀器的顯示器顯示出來。從比較兩 個信號的輸出，控制邏輯向上 /向下計數(shù)器產(chǎn)生了。s two input frequencies, the unknown one and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier. When DDS output (fDDS) has approached fin, due to hysteresis, no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1 and f2 are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequency modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digitaltoanalog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D mand (input) to the counter while the upper trace is a hypothetical frequency modulating waveform. It is obvious that the term hypothetical is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is 177。s maximum count. The major blocks have been shown . Among them are the Frequency Comparator and the DDS. To overe some disadvantages of the specific frequency parator a correction stage has been incorporated. This stage is also used for the measurement extraction in order to display the correct reading. Operation of the circuit The circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it39。s output acting as the Frequency Setting Word (FSW) instructs the DDS to produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associated stages up to the instrument39。s inputs. The FC accepts the hardlimited waveform of the DDS as well as the unknown frequency. From the parison of the two signals a logic output that controls an up/down counter is produced. The counter39。 If n the phase step is equal to one, the accumulator will count by ones, taking 2 clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator counting by twos, taking 2n?1 clock cycles to plete one n?1 cycle of the output sinewave. It can easily be shown that for any integer m, where m 2 , the number of clock cycles taken to generate one cycle of the output sine wave is 2n /m, and the output frequency (fDDS) and the frequency resolution (fres) are given by the following formulas： m fclk 2n n fres= fclk/ 2 fDDS= For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is mHz. If n is increased to