【正文】 or automatically. Interrupts automatically reset this bit, and the reti instruction automatically sets it. 1=Interrupts Enabled 0=Interrupts Disabled ? The CPU off bit (CPUOff) Location: SR(4) Function: Enables or disables the CPU core. Can be cleared by software, and is reset by enabled interrupts. None of the memory, peripherals, or clocks are affected by this bit. This bit is used as a power saving feature. 1=CPU is on 0=CPU is off ? The Oscillator off bit (OSCOff) Location: SR(5) Function: Enables or disables the crystal oscillator circuit (LFXT1). Can be cleared by software, and is reset by enabled external interrupts. OSCOff shuts down everything, including peripherals. RAM and register contents are preserved. This bit is used as a power saving feature. 1=LFXT1 is on 0=LFXT1 is off ? The System Clock Generator (SCG1,SCG0) Location: SR(7),SR(6) Function: These bits, along with OSCOff and CPUOff define the power mode of the device. ? The Overflow Flag (V) Location: SR(8) Function: I dentifies when an operation results in an overflow. Can be set or cleared by software, or automatically. Overflow occurs when two positive numbers are added together, and the result is negative, or when two negative numbers are added together, and the result is positive. 1=Overflow result occurred 0=No overflow result occurred Four of these flags (Overflow, Negative, Carry, and Zero) drive program control, via instructions such as cmp (pare) and jz (jump if Zero flag is set). You will see these flags referred to often in this book, as their function represents a fundamental building block. The instruction set is detailed in Chapter 9, and each base instruction description there details the interaction between flags and instructions. As a programmer, you need to understand this interaction. Stack Pointer The Stack Pointer is implemented in R1. Like the Program Counter, the LSB is fixed as a zero value, so the value is always even. The stack is implemented in RAM, and it is mon practice to start the SP at the top (highest valid value) of RAM. The push mand moves the SP down one word in RAM (SP=SP2), and puts the value to be pushed at the new SP. Pop does the reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value from the TOS (top of stack) back into the PC. I have one simple rule of thumb for the SP: leave it alone. Set the stack pointer as part of your initialization, and don39。multiply R15 by two,since PC is always even Rla R15 。t know today what the values in R8, R9 and R15 represent. This was code I wrote to quickly validate an algorithm, rather than production code, so I didn39。430 is petitive in price with the 8bit controller market, and supports both 8 and 16bit instructions, allowing migration from most similarly sized platforms. The family of devices ranges from the very small (1k ROM, 128 bytes for RAM, subdollar) up to larger (60k ROM, 2k RAM, with prices in the $10 range) devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is a basic unit, the MSP430x1xx, which is a more featurerich family, and the MSP430x4xx, which is similar to the 39。430 family. It consists of a 3stage instruction pipeline, instruction decoding, a 16bit ALU, four dedicateduse registers, and twelve working (or scratchpad) registers. The CPU is connected to its memory through two 16bit busses, one for addressing, and the other for data. All memory, including RAM, ROM, information memory, special function registers, and peripheral registers are mapped into a single, contiguous address space. This architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains available for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented. Second, there are plenty of working registers. After years of having one or two working registers, I greatly enjoyed my first experience with the twelve 16bit CPU scratchpads. The programming style is slightly different, and can be much more efficient, especially in the hands of a programmer who knows how to use this feature to its fullest. Third, this architecture is deceptively straightforward. It is very flexible, and the addressing modes are more plicated than most other small processors. But, beyond that, this architecture is simple, efficient and clean. There are two busses, a single linear memory space, a rather vanilla processor core, and all peripherals are memorymapped. CPU Features The ALU The 39。if R157,do not use PC switch Cmp 0,R15 。BAR 。 這也是需重要注意到，雖然在這本書的大部分信息與現(xiàn)成的 TI 的文件是相同的，這本書的目的是 補充，而不是替代的寶貴的信息來源。 目前，至少有 40 個可用，更 經常被規(guī)律添 加。 所有設備部件編號按照以下模板： MSP430Mt Fa F bMc M:內存類型 C: ROM F: Flash P: OTP E: EPROM (為推導使用 . 有以下幾種 .) F a, F b: 系列和結 構 10, 11: 基本 12, 13: 硬件串口 14: 硬件串口 , 硬件乘法器 31, 32: LCD 控制器 33: LCD 控制器 , 硬件串口 , 硬件乘法器 41: LCD控制器 43: LCD控制器 , 硬件串口 44: LCD 控制器 , 硬件串口 , 硬件乘法器 Mc: 電容存儲器 3 0: 1kb ROM, 128b RAM 1: 2kb ROM, 128b RAM 2: 4kb ROM, 256b RAM 3: 8kb ROM, 256b RAM 4: 12kb ROM, 512b RAM 5: 16kb ROM, 512b RAM 6: 24kb ROM, 1kb RAM 7: 3