單片機(jī)設(shè)計(jì)--畢業(yè)設(shè)計(jì)外文翻譯(存儲(chǔ)版)
【正文】 direction for the control of a singlechip core design requirements of a multifunction indicators in line with the digital clock. The design is based on the principle of singlechip technology to chip AT89C52singlechip microputer as the core controller, through the production of hardware and software procedures for the preparation, design to produce a multifunctional digital clock system. The clock system mainly by clock module, alarm module, the ambient temperature detectio n module, liquid crystal display module, control module and the keyboard signal prompted module. System is simple and clear user interface that can 4V ~ 7V DC power under normal operation. Able to accurately display time (display format hh: mm: seconds seconds, 24hour system), may be time to adjust at any time, with clock time settings, alarm on / off, only to make functions, where the clock to measure the ambient temperature and displayed. Hardware and software design into the guiding ideology, give full play to the singlechip features, most of the functions through software programming to achieve, the circuit is simple and clear, high system stability. At the same time, the clock 畢業(yè)設(shè)計(jì)（論文） 3 system also has the power of small, low cost, and highly practical. System ponents as a result of less use, singlechip occupied by the I / O port not more than, the system has a certain degree of scalability. Clock design is no theory of discrete logic, programmable logic, or using fullcustom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poor design of the clock in the limits of temperature, voltage deviation or the manufacturing process will result in the case wrong, and debugging difficult, spending a lot. In the desi gn of FPGA / CPLD clock when several types of monly used. Clock can be divided into the following four types: global clock, clock gating, multilevel logic clock clock and volatility. Multiclock system to include the abovementioned four types of any bination of the clock. No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal clock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the practical work as expected . Clock in the actual model, we have to consider the spread of clocktree skew, vertical jump and absolute bias and other uncertainties. To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure tha
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