單片機(jī)設(shè)計--畢業(yè)設(shè)計外文翻譯(已改無錯字)
2023-01-06 04:26:41 本頁面
【正文】 vidence of the reliability of the design of the project has bee very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not use multilevel binational logic to clock the flipflop in the PLD design. Travelingwave clock clock another popular use of travelingwave circuit is the clock, that is, the output of a flipflop used as a clock input of another flipflop. If careful design, travelingwave clock can be the same as the global clock to work reliably. However, the travelingwave clock made from time to time with the calculation of the circuit bees very plicated. Linewave travelingwave clock flipflop of the chain have a greater clock time between the offset and exceed the worst case the setup time, hold time and clock to the 畢業(yè)設(shè)計（論文） 5 output circuit of the delay, allowing the system to the actual slowed down. Multiclock system, many system requirements within the same multiPLD clock. The most mon example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous munication channel interface. As the clock signal between the two requirements to establish and maintain a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal. In many applications, only the synchronization of asynchronous signals is not enough, when the system of two or more nonhomologous clock, the data it is difficult to establish and maintain the time to be assured that we will face the plex matter of time . The best way is to all nonhomologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PLL, DLL, and chip PLL with most expensive, so unless there are special requirements, the general occasions PLL can not use with the this time we need to take to enable the use of the D flipflopside, and the introduction of a highfrequency clock. 畢業(yè)設(shè)計（論文） 6 采用 L ED 數(shù)碼管的數(shù)字顯示以其亮度高、顯示直觀等優(yōu)點(diǎn)被廣泛應(yīng)用于智能儀器及家用電器等領(lǐng)域 . 本文介紹一種以 AT89C52單片機(jī)為核心 ,以共陽極高亮度 L ED 數(shù)碼管作為顯示器件組成 7 位數(shù)字顯示的實(shí)用多功能電子時鐘的設(shè)計 ,該時鐘可顯示星期、時、分、秒 ,也可切換為年、月、日顯示 ,同時具有整點(diǎn)音樂報時及定時鬧鐘等功能 ,也可作電子秒表使用。 時鐘電路是計算機(jī)的心臟 , 它控制著計算機(jī)的工作節(jié)奏就是通過復(fù)雜的時序電路完成不同的指令功能的。 時鐘，自從它被發(fā)明的那天起，就成為人們生活中必不可少的一種工具，尤其是在現(xiàn) 在這個講究效率的年代，時鐘更是在人類生產(chǎn)、生活、學(xué)習(xí)等多個領(lǐng)域得到廣泛的應(yīng)用。然而隨著時間的推移，人們不僅對于時鐘精度的要求越來越高，而且對于時鐘功能的要求也越來越多，時鐘已不僅僅是一種用來顯示時間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。諸如鬧鐘功能、日歷顯示功能、溫度測量功能、濕度測量功能、電壓測量功能、頻率測量功能、過欠壓報警功能等。鐘表的數(shù)字化給人們
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