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畢業(yè)設(shè)計(jì)---基于單片機(jī)的出租車計(jì)價(jià)器的設(shè)計(jì)-預(yù)覽頁

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【正文】 還需要按鍵手動(dòng)復(fù)位 (圖 ) 。 圖 復(fù)位 電路 畢業(yè)設(shè)計(jì) 第 頁 8 掉電保護(hù)電路 掉電保護(hù)電路中采用了存儲(chǔ)芯片 AT24C02。 A1(引腳 2):器件地址的 A1 位。 SCL(引腳 6): 時(shí)鐘總線引腳。其實(shí)只需在時(shí)鐘引腳連接上外圍的定時(shí)控制元件,就可以構(gòu)成一個(gè)穩(wěn)定的自激振蕩器。 如圖 所示。 另外為功能鍵,控制價(jià)格調(diào)整,這個(gè)按鍵是在沒有按下啟動(dòng) /停止按鍵時(shí)有作用,計(jì)價(jià)過程中無效。 C語言編寫的程序,雖然不象匯編那樣速度快、但程序簡單易行、并且需要較小的存儲(chǔ)空間。 本設(shè)計(jì)就是采用 C 語言編寫的,由于采用模塊化操作,使得程序在修改,執(zhí)行的時(shí)候顯得方便易行。 這些對(duì)應(yīng)于硬件就 是通過按下各個(gè)控制開關(guān),來分別進(jìn)行不同的動(dòng)作,最后數(shù)碼管根據(jù)輸入的信息,來顯示不同的數(shù)據(jù)信息,這就達(dá)到了軟件控制硬件,同時(shí)輸入信息控制輸出信息的目的。 調(diào)試的一般過程如圖 所示: 圖 系統(tǒng)調(diào)試流程圖 系統(tǒng)調(diào)試的一般過程是上電運(yùn)行后觀察其運(yùn)行狀態(tài),數(shù) 碼管是否點(diǎn)亮等。 程序調(diào)試工具 — KEIL 本 設(shè)計(jì)的軟件都是在 Keil μ Vision 上進(jìn)行編寫,編譯,調(diào)試以及運(yùn)行操作。 ,進(jìn)行軟件仿真調(diào)試,直到出現(xiàn)正確的結(jié)果。 對(duì)于畢業(yè)設(shè)計(jì) 第 頁 14 數(shù)碼管 的檢測在顯示電路中已介紹。 常用排阻 有 A 型和 B 型。它沒有公共端,常見的排阻有 4個(gè)電阻,所以引腳共有 8個(gè)。 元件的焊接方法 手 工焊接是傳統(tǒng)的 的焊接方法, 雖然批量電子產(chǎn)品生產(chǎn)已較少采用手工焊接了 ,但 在電 子產(chǎn)品的維修、調(diào)試中不可避免地還會(huì)用到手 工焊接。焊接元器件及維修電路板時(shí)以握筆式較為方便。若是要拆下印刷板上的元器件 ,則待烙鐵頭加熱后 ,用手或 鑷子輕輕拉動(dòng)元器件 ,看是否可以取下。 二、焊接質(zhì)量不高的原因 手工焊接對(duì)焊點(diǎn)的要求是: ① 電連接性能良好; ② 有一定的機(jī)械強(qiáng)度; ③ 光滑圓潤。 ③ 夾松香焊接 ,焊錫與元器件或印刷板之間夾雜著一層松香 ,造成電連接不良。 ④ 焊錫連橋。當(dāng)少量松香殘留時(shí) ,可以用電烙鐵再輕輕加熱一下 ,讓松香揮發(fā)掉 ,也可以用蘸有無水酒精的棉球 ,擦去多余的松香或焊劑。易損元器件在焊接前要認(rèn)真作好表面清潔、鍍錫等準(zhǔn)備工作 ,焊接時(shí)切忌長時(shí)間反復(fù)燙焊 ,烙鐵頭及烙鐵溫度要選擇適當(dāng) ,確保一次焊接成功。焊接集成電路最好先焊接地端、輸出端、電源端 ,再焊輸入端。 焊接過程中 要特別注意的幾點(diǎn): ( 1) 在 焊接 多引腳 元件時(shí)最好焊 接一個(gè)底 座,這樣可以避免 器件 燒壞。 硬件檢測 設(shè)計(jì)的過程中,對(duì)硬件的檢測和對(duì)軟件的測試都不能忽略,因?yàn)樵谙到y(tǒng)的仿真過程中。 在已經(jīng)焊接好的電路板上 ,要對(duì)其各個(gè)元器件進(jìn)行檢查。 元件在選購時(shí)需要 多備選元件 ,元件的型號(hào)較多, 產(chǎn)品質(zhì)量沒有可靠保證, 就避免不了我們買的元器件是損壞的,再加上焊接是在萬能板上焊接的。 驅(qū)動(dòng)部分是檢查 74LS245 與數(shù)碼管和單片機(jī)接觸的各個(gè)引腳,看是否焊接良好,另外要讓芯片和插座 有 良好的接觸。如果出現(xiàn)看不到 12MHZ 的正弦波形的現(xiàn)象,說明此部分電路不正常 。在設(shè)計(jì)開始,要形成流程圖,它可以使設(shè)計(jì)有一定的邏輯性與嚴(yán)密性,使得設(shè)計(jì)思路明確。本次設(shè)計(jì)我學(xué)習(xí)到不少單片機(jī)的知識(shí),但由于自己的理論知識(shí)水平有限,實(shí)踐知識(shí)和設(shè)計(jì)經(jīng)驗(yàn)不足,在設(shè)計(jì)過程中難免存在一些問題。作為一個(gè)本科生的畢業(yè)設(shè)計(jì),由于沒有 足夠 的經(jīng)驗(yàn),難免有諸多考慮不周的地方, 好 在 有導(dǎo)師的指導(dǎo)和同學(xué)們的幫助,我才能 按時(shí)完成任務(wù) 。 畢業(yè)設(shè)計(jì)培養(yǎng)了我們獨(dú)立思考問題 ,分析 問題與解決問題的能力,在設(shè)計(jì)中我明白了理論與實(shí)踐有很大的區(qū) 別,理論上可以實(shí)現(xiàn)的,但要做具體的實(shí)物,卻要多方面考慮。在此謹(jǐn)向 老師致以誠摯的感謝。 for 42PDIP GND connects only the logic core and the embedded program memory). VDD: Supply voltage for the 42PDIP which connects only the logic core and the embedded program memory. PWRVDD: Supply voltage for the 42PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage. PWRGND: Ground for the 42PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the mon silicon substrate, but not through 畢業(yè)設(shè)計(jì) 第 頁 22 any metal link. The application board MUST connect both GND and PWRGND to the board ground. Port 0: Port 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, PO has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pullups. Port 2: Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that uses 16bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register. 畢業(yè)設(shè)計(jì) 第 頁 23 Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3: Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pullups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table. RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise
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