數(shù)字時(shí)鐘外文翻譯-全文預(yù)覽
【正文】 n of the project has bee very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not use multilevel binational logic to clock the flipflop in the PLD design. Travelingwave clock clock another popular use of travelingwave circuit is the clock, that is, the output of a flipflop used as a clock input of another flipflop. If careful design, travelingwave clock can be the same as the global clock to work reliably. However, the travelingwave clock made from time to time with the calculation of the circuit bees very plicated. Linewave travelingwave clock flipflop of the chain have a greater clock time between the offset and exceed the worst case the setup time, hold time and clock to the output circuit of the delay, allowing the system to the actual slowed down. Multiclock system, many system requirements within the same multiPLD clock. The most mon example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous munication channel interface. As the clock signal between the two requirements to establish and maintain a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal. In many applications, only the synchronization of asynchronous signals is not enough, when the system of two or more nonhomologous clock, the data it is difficult to establish and maintain the time to be assured that we will face the plex matter of time . The best way is to all nonhomologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PLL, DLL, and chip PLL with most expensive, so unless there are special requirements, the general occasions PLL can not use with the this time we need to take to enable the use of the D flipflopside, and the introduction of a highfrequency clock. 采用L ED 數(shù)碼管的數(shù)字顯示以其亮度高、顯示直觀等優(yōu)點(diǎn)被廣泛應(yīng)用于智能儀器及家用電器等領(lǐng)域. 本文介紹一種以AT89C52單片機(jī)為核心,以共陽(yáng)極高亮度L ED 數(shù)碼管作為顯示器件組成7 位數(shù)字顯示的實(shí)用多功能電子時(shí)鐘的設(shè)計(jì),該時(shí)鐘可顯示星期、時(shí)、分、秒,也可切換為年、月、日顯示,同時(shí)具有整點(diǎn)音樂(lè)報(bào)時(shí)及定時(shí)鬧鐘等功能,也可作電子秒表使用。諸如鬧鐘功能、日歷顯示功能、溫度測(cè)量功能、濕度測(cè)量功能、電壓測(cè)量功能、頻率測(cè)量功能、過(guò)欠壓報(bào)警功能等。在很多實(shí)際應(yīng)用中，只要對(duì)數(shù)字時(shí)鐘的程序和硬件電路加以一定的修改，便可以得到實(shí)時(shí)控制的實(shí)用系統(tǒng)，從而應(yīng)用到實(shí)際工作與生產(chǎn)中去。高精度、多功能、小體積、低功耗，是現(xiàn)代時(shí)鐘發(fā)展的趨勢(shì)。該時(shí)鐘系統(tǒng)主要由時(shí)鐘模塊、鬧鐘模塊、環(huán)境溫度檢測(cè)模塊、液晶顯示模塊、鍵盤(pán)控制模塊以及信號(hào)提示模塊組成。同時(shí)，該時(shí)鐘系統(tǒng)還具有功耗小、成本低的特點(diǎn)，具有很強(qiáng)的實(shí)用性。在設(shè)計(jì)FPGA/CPLD時(shí)通常采用幾種時(shí)鐘類型。在實(shí)際的時(shí)鐘模型中，我們要考慮時(shí)鐘樹(shù)傳播中的偏斜、跳變和絕對(duì)垂直的偏差以及其它一些不確定因素。在PLD/FPGA設(shè)計(jì)中最好的時(shí)鐘方案是：由專
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