【正文】 area of frequency.This frequency meter uses CPLD to realize the measuring count of frequency. Single chip puter pletes the test control、data processing and display output of the system.This essay discusses the pose of hardware circuit and software control flow of single chip puter in detail. Hardware circuit includes key control module、display module, plastic module of input signal、single chip puter control module and CPLD main control module.The frequency meter adopts single chip puter AT89C51 of Atmel pany and EPM7128SLC8415 of Altera pany. Key control module has 1 function key and 3 time selection key. A chip 74LS165 pletes the key value input. Display module uses eight 74LS165s to realize the serial display of LED. First, the measuring signal amplitude is limited. Second, the single is amplified by two class direct coupling amplifier. Finally, the signal inputs CPLD after it is trimed by Smitter trigger. Standard frequency is 40MHZ. Software program of single chip puter is writed by assembly language. Some of software program is corresponded to every hardware part, the others includ data count and transform.Key Words：SCM。 Equalprecision目錄摘要 .............................................................IABSTRACT ........................................................II1 緒論 ..........................................................1 頻率計(jì)基礎(chǔ)知識 ...............................................1 對靈敏度和準(zhǔn)確度的要求 .............................................................................1 測量儀器的準(zhǔn)確度的選擇 .............................................................................2 微波計(jì)數(shù)器的使用 .........................................................................................2 技術(shù)背景及發(fā)展趨勢 ...........................................3 EDA 技術(shù)的發(fā)展及其應(yīng)用 .......................................4 單片機(jī)概論 ...................................................5 頻率計(jì)的設(shè)計(jì)內(nèi)容和意義 .......................................62 設(shè)計(jì)理論基礎(chǔ) ..................................................8 CPLD/FPGA 設(shè)計(jì)意義 ...........................................8 EDA..................................................................................................................8 CPLD(復(fù)雜可編程邏輯器件) .......................................................................8 FPGA（現(xiàn)場可編程門陣列） ......................................................................9 FPGA 和 CPLD 的選擇 .................................................................................9 頻率測量原理 .................................................9 頻率測量 .......................................................................................................10 周期測量 .......................................................................................................10 等精度測頻法 ...............................................................................................11 方案設(shè)計(jì) ....................................................13 基于單片機(jī)的方案 .......................................................................................13 基于 CPLD/FPGA 和單片機(jī)相結(jié)合的方案 .............................................14 方案論證與選擇 ...........................................................................................153 單元模塊設(shè)計(jì) .................................................16 系統(tǒng)組成 ....................................................16 鍵控制模塊 ..................................................17 串行輸出移位寄存器（74LS165 ） .........................................................17 鍵盤電路 .......................................................................................................18 顯示模塊 ....................................................19 顯示電路設(shè)計(jì) ...............................................................................................19 74LS164(串入并出移位寄存器) ...............................................................21 電源模塊 ....................................................21 輸入信號整形模塊 ............................................22 信號整形電路 ...............................................................................................22 施密特觸發(fā)器 ...............................................................................................23 單片機(jī)主控模塊 ..............................................24 AT89C51 單片機(jī)性能 ................................................................................24 單片機(jī)控制電路 ...........................................................................................31 測頻模塊的工作原理及設(shè)計(jì) ....................................32 CPLD 的結(jié)構(gòu)與功能介紹 ...........................................................................32 CPLD 引腳分布 ............................................................................................33 CPLD 模塊邏輯設(shè)計(jì) ...................................................................................3438 其它電路 ....................................................354 軟件設(shè)計(jì) .....................................................36 MAS+PLUSⅡ概述 ...............................................36 MAX+PLUSⅡ使用 VHDL 實(shí)現(xiàn)系統(tǒng)功能的全過程 ......................36 電子系統(tǒng)的設(shè)計(jì)方法 ..................................................................................36 “自頂向下 ”與“自底向上”的設(shè)計(jì)方法 .............................................37 VHDL 語言簡介 ...........................................................................................39 頻率計(jì)的 VHDL 設(shè)計(jì) .................................................................................39 CPLD 模塊仿真 ...............................................41 下載驗(yàn)證 ....................................................41 單片機(jī)的匯編語言編程 ........................................42 單片機(jī)主程序 ...............................................................................................42 測頻子程序 ...................................................................................................43 顯示子程序 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