【正文】 , the traditional manual design state machines have been impossible, and FPGAbased VHDL language to describe the state machine is a general trend. FPGAbased hardware description language designed to take full advantage of A / D sampling speed, highperformance, higher efficiency and accuracy. Key words: EDA VHDL FPGA state machine digital display 目錄 第一章 ：緒論 ................................................................................................................... 1 研究目的及意義： ............................................................................................... 1 國(guó)內(nèi)外同類研究概況： ........................................................................................ 1 研究?jī)?nèi)容： .......................................................................................................... 2 第二章： EDA 技術(shù)及其開(kāi)發(fā)工具簡(jiǎn)介 ............................................................................... 3 EDA 技術(shù)簡(jiǎn)介 ..................................................................................................... 3 Quartus 簡(jiǎn)介 ........................................................................................................ 3 設(shè)計(jì)的基本邏輯門例子 ....................................................................................... 4 本章小結(jié) ........................................................................................................... 6 第三章： VHDL 語(yǔ)言基礎(chǔ) ................................................................................................. 7 VHDL 語(yǔ)言簡(jiǎn)介 ................................................................................................... 7 VHDL 語(yǔ)言設(shè)計(jì)例子 ............................................................................................ 7 本章小結(jié) ............................................................................................................ 8 第四章： FPGA 基礎(chǔ) ......................................................................................................... 9 CPLD 分類 ........................................................................................................... 9 FPGA 簡(jiǎn)介 ........................................................................................................... 9 本章小結(jié) .......................................................................................................... 11 第四章：有限狀態(tài)機(jī)的基本概念 ..................................................................................... 12 有限狀態(tài)機(jī)設(shè)計(jì)硬件的優(yōu)勢(shì) ............................................................................... 12 有限狀態(tài)機(jī)的設(shè)計(jì)的一個(gè)代碼例子 .................................................................... 12 狀態(tài)機(jī)的時(shí)序邏輯進(jìn)程 ...................................................................................... 13 本章小結(jié) ...................................................................................................... 14 第五章：基于 FPGA 的采樣狀態(tài)機(jī) ................................................................................. 15 設(shè)計(jì)總體思路 ................................................................................................... 15 采樣模塊的設(shè)計(jì) ................................................................................................ 15 AD0809 的整體功能說(shuō)明 ........................................................................ 15 0809 的引腳功能說(shuō)明 ............................................................................... 16 AD0809 的 VHDL 語(yǔ)言說(shuō)明 ................................................................... 17 分頻模塊 .......................................................................................................... 19 顯示模塊 .......................................................................................................... 19 程序及仿真 ....................................................................................................... 20 程序 ........................................................................................................ 20 仿真及原理圖 .......................................................................................... 27 本章小結(jié) .......................................................................................................... 28 總結(jié) ............................................................................