【正文】 頂向下和基于庫的設(shè)計(jì)的特點(diǎn)，因此設(shè)計(jì)者可以不必了解硬件結(jié)構(gòu)。而集成電路 (IC)技術(shù)在微電子領(lǐng) 域占有重要的地位。 then it introduces the system design of digital frequency meter, and the realization of frequency meter each system module VHDL. Finally using QUARTUSⅡ integrated development environment edits, synthesizes, and simulates, and download to the CPLD devices, by using the actual circuit testing, simulation and experimental results show that this frequency meter is high availability and reliability. Keywords: EDA。 本課題的數(shù)字頻率計(jì)設(shè)計(jì)，采用自上向下的設(shè)計(jì)方法?；?EDA 技術(shù)和硬件描述語言的自上而下的設(shè)計(jì)技術(shù)正在承擔(dān)起越來越多的數(shù)字系統(tǒng)設(shè)計(jì)任務(wù)。s technology. The topdown design techniques based on EDA technology and hardware description language are taking on more and more digital system design task. The topic digital frequency meter design uses topdown design approach. First, this paper summarizes the overview of EDA technology, then it describes the hardware description language which is called VHDL, FPGA programmable device and the general principles of frequency measurement。 VHDL language 目 錄 1 引言 ................................................................................................................................ 1 2 硬件描述語言（ HDL） ................................................................................................ 2 語言簡介 .............................................................................................. 2 利用 VHDL 語言開發(fā)的優(yōu)缺點(diǎn) .......................................................................... 3 3 電子設(shè)計(jì)自動化（ EDA）發(fā)展概述 ............................................................................ 4 EDA 的簡介 .......................................................................................................... 4 EDA 的發(fā)展史 ...................................................................................................... 4 基于 EDA 的 FPGA/CPLD 開發(fā) .......................................................................... 5 FPGA/CPLD 的簡介 .................................................................................... 6 用 FPGA/CPLD 進(jìn)行開發(fā)的優(yōu)缺點(diǎn) .......................................................... 7 4 頻率 計(jì)的 測量 及方案選擇 ............................................................................................ 9 數(shù)字頻率計(jì)工作原理概述 .................................................................................. 9 測頻原理及誤差分析 ........................................................................................ 10 常用測頻方案 ............................................................................................ 10 等精度測頻原理 ....................................................................................... 10 誤差分析 .................................................................................................... 11 5 數(shù)字頻率計(jì)的系統(tǒng)設(shè)計(jì)與功能仿真 .......................................................................... 13 系統(tǒng)的總體設(shè)計(jì) ................................................................................................ 13 頻率計(jì) 模塊 ........................................................................................................ 14 測頻控制模塊 ......................................................................................... 14 鎖存器模塊 ............................................................................................. 15 十進(jìn)制計(jì)數(shù)器模塊 ................................................................................. 16 顯示模塊 ............................................................................................................ 17 顯示模塊設(shè)計(jì) .......................................................................................... 17 譯碼器 模塊 .............................................................................................. 18 四位二進(jìn)制數(shù)與十六位二進(jìn)制數(shù)轉(zhuǎn)換的源程序 .................................. 19 十六位二進(jìn)制數(shù)與四位二進(jìn)制數(shù)轉(zhuǎn)換的源程序 .................................. 19 四位二進(jìn)制數(shù)與段碼轉(zhuǎn)換的源程序 ...................................................... 21 6 整形電路設(shè)計(jì) .............................................................................................................. 22 555 定時器的工作原理 ...................................................................................... 22 施密特觸發(fā)器 .................................................................................................... 23 電路結(jié)構(gòu) ................................................................................................. 23 工作原理 ............................................................................................... 23 波形的整形 ......................................................................................................... 24 7 軟件測試及硬件下載 .................................................................................................. 25 QuartusII 軟件簡介 ............................................................................................. 25 QuartusII 的設(shè)計(jì)流程 ......................................................................................... 25 QuartusII 軟件的使用方法 ................................................................................. 26 創(chuàng)建底層模塊 ....................................................................................... 26 構(gòu) 建頂層模塊 ....................................................................................... 30 下載及硬件實(shí)現(xiàn) ................................................................................................ 32 8 結(jié) 論 .............................................................................................................................. 34 謝辭 .................................................................................................................................. 35 參考文獻(xiàn) .......................................................................................................................... 36 附錄 Ⅰ 頻率計(jì)頂層文件 .....