【正文】 重要的 CAD工具用于將每個(gè)電路架構(gòu)，以地圖的高品質(zhì)展現(xiàn)。在第 5節(jié)講述了比較有必要的 VPR曲目數(shù)量和該電路成功的布線所要求的其他已發(fā)表的工具。 VPR可以放置電路，或一個(gè)預(yù)先存在的位置，可以讀入 VPR 可以執(zhí)行或者是全局的路線或合并后的全球 /詳細(xì)的安置途徑。最后，如 果合并后的全球和詳細(xì)的路由被執(zhí)行，一個(gè)也會(huì)進(jìn)行求值： ?開關(guān)塊 [1]架構(gòu)（即為何路由曲目是相互關(guān)聯(lián)的）， ?曲目號碼，每個(gè)邏輯塊的輸入引腳連接（ [1]）， ?為邏輯塊輸出 FC值， ?對 I / O口 FC值。路由器，圖形可視化和統(tǒng)計(jì)計(jì)算程序都與此路由資源圖的工作相關(guān)，所以添加新的路由架構(gòu)功能僅涉及更改的子程序來建設(shè)這個(gè)圖。 VPACK邏輯塊包裝程序 /網(wǎng)絡(luò)表翻譯 VPACK讀取一個(gè)已 經(jīng)技術(shù)映射電路網(wǎng)表格式 blif 到 LUT和觸發(fā)器，包裝成所需的 FPGA邏輯 LUT和觸發(fā)器塊，并輸出在 VPR的網(wǎng)表。 3 布局算法 VPR采用模擬退火算法 [7]。邊界線長度模型中的實(shí)際低估所需的布線，就可以看成超過三個(gè)終端網(wǎng)，作為建議 [10]。本文中的所有結(jié) 果的得到，是利用 FPGA中的所有通道都有相同的原則。我們計(jì)算在初始溫度相同的方式為 [11]。初始溫度設(shè)定為 20倍標(biāo)準(zhǔn)差，確保最初幾乎所有的行動(dòng)是在退火算法范圍內(nèi)被系統(tǒng)接受。當(dāng)溫度是如此之高，幾乎任何舉動(dòng)都可以被接受時(shí)，我們基本上從一個(gè)位置隨機(jī)移動(dòng)到另一個(gè)位置所改善獲得的成本都是小成本。為此，就需要利用 Raccept值來控制這個(gè)范圍限制器。最初， Dlimit設(shè)置為整個(gè)芯片。 4路由算法 VPR的路由器是基于試探談判的擁塞算法 [14， 8]。通過逐漸增加的多余認(rèn)購路由資源成本，該算法勢力替代路線網(wǎng)，以避免使用超額認(rèn)購資源，只剩下網(wǎng)最需要一個(gè)給定的資源。無論是原探路者算法和 Vpr 路由器使用的 Dijkstra 算法（即一個(gè)迷宮路由器 [15]），以每個(gè)網(wǎng)絡(luò)連接和AK用線網(wǎng)為依據(jù)，路由器調(diào)用通道的 k 1次執(zhí)行所有需要的連接。之后的 K 1路由器的迷宮調(diào)用凈終端將所有 k值連接。幸好，有一個(gè)更有效的方法。圖 3說明了差異圖形。每個(gè) LUT的輸入出現(xiàn)在一個(gè)邏輯塊的一面，而邏輯塊輸出一般訪問底部和右側(cè)，如圖4。如果輸入引腳之間的音軌和它連接接線盒的 Fc 通過獨(dú)立的 SRAM位控制晶體所組成，為了驗(yàn)證兩條軌道上的這些開關(guān)通過電氣連接的可能性。因此，如果在未來 FPGA的路由器測試時(shí)沒有輸入引腳 doglegs 那么我們必須讓輸入引腳 doglegs 和過去 的結(jié)果公平的比較這樣是最好的。 VPR要求比第二，第三最 佳路由器降低 10％的資源數(shù)目，表 3列出了音軌需要執(zhí)行這些標(biāo)準(zhǔn)時(shí)數(shù)新的 CAD工具，同時(shí)允許地方和路線的電路的連接。最后，讓 VPR配置電路而不是強(qiáng)迫它使用 Altor 內(nèi)存來減少資源數(shù)目的 40％，這表明 VPR的模擬退火算法單元遠(yuǎn)較 Altor 最小單元更好。無論是基于 VPR和 SPLACE只要是使用模擬退火算法，我們相信 VPR單元在一方面優(yōu)于 SPLACE是因?yàn)樗幚砀呱瘸鼍W(wǎng)絡(luò)更有效率，讓更多的動(dòng)作進(jìn)行評估，另一方面是因?yàn)樗行У耐嘶饡r(shí) 間表給定的時(shí)間。 I / O引腳數(shù)每行或列適合設(shè)置為 2，符合目前的商業(yè)化 FPGA。在世嘉列中的條目 179。因?yàn)槁酚纱箅娐樊?dāng)輸入引腳 doglegs 是不允許的。該技術(shù)映射網(wǎng)表，由 VPR生成和投放位置的目前最全的跟蹤路由在 jayar / 。我們希望下一代的 FPGACAD工具將優(yōu)化這些大型基點(diǎn)，因?yàn)樗麄兪且幌盗忻芮械膯栴}被映射成今天的 FPGA。 10 外文原文 VPR: A New Packing， Placement and Routing Tool for FPGA Research1 Vaughn Betz and Jonathan Rose Department of Electrical and Computer Engineering， University of Toronto Toronto， ON， Canada M5S 3G4 {vaughn， Abstract We describe the capabilities of and algorithms used in a new FPGA CAD tool，Versatile Place and Route (VPR). In terms of minimizing routing area， VPR outperforms all published FPGA place and route tools to which we can the algorithms used are based on previously known approaches， we present several enhancements that improve runtime and quality. We present placement and routing results on a new set of large circuits to allow future benchmark parisons of FPGA place and route tools on circuit sizes more typical of today’s industrial is capable of targeting a broad range of FPGA architectures， and the source code is publicly available. It and the associated list translation /clustering tool VPACK have already been used in a number of research projects worldwide， and should be useful in many areas of FPGA architecture research. 1 Introduction In FPGA research， one must typically evaluate the utility of new architectural features experimentally. That is， benchmark circuits are technology mapped， placed and routed onto the FPGA architectures of interest， and measures of the architecture’s quality， such as speed or area， can then readily be extracted. Accordingly， there is considerable need for flexible CAD tools that can target a wide variety of FPGA architectures efficiently， and hence allow fair parisons of the paper describes the Versatile Place and Route (VPR) tool， which has been designed to be flexible enough to allow parison of many different FPGA can perform placement and either global routing or bined global anddetailed routing. It is publicly available from 11 In order to make meaningful FPGA architecture parisons， it is essential that the CAD tools used to map circuits into each architecture are of high quality. The routing phase of VPR outperforms all previously published FPGA routers for which standard benchmarks results are available， and that the bination of VPR’s placer and router outperforms all published binations of FPGA placement and routing The organization of this paper is as follows. In Section 2 we describe some of the features of VPR and the range of FPGA architectures with which it may be used. In Sections 3 and 4 we describe the placement and routing algorithms. In Section 5， we pare the number of tracks required by VPR to successfully route circuits with that required by other published tools. In Section 6 we conclude and outline some future enhancements which will be made to VPR. 2 Overview of VPR Figure 1 outlines the VPR CAD flow. The inputs to VPR consist of a technologymapped list and a text file describing the FPGA architecture. VPR can place the circuit， or a preexisting placement can be read in. VPR can then perform either a global route or a bined global/detailed route of the placement. VPR’s output consists of the placement and routing， as well as statistics useful in assessing the utility of an FPGA architecture， such as routed wirelength， track count， and maximum of the architectural parameters that can be specified in the architecture description file are: ? the number of logic block inputs and outputs， ? the side(s) of the logic block from which each input and output is accessible， ? the logical equivalence between various input and output pins (. all LUT inputs are functionally equivalent)， ? the number of I/O pads that fit into one row or one column of the FPGA， and ? the dimensions of the logic block array (. 23 x 30 logic blocks). In addition， if global routing is to be performed， one can also specify: ? the relative widths of horizontal and vertical channels， and ? the relative widths of the channels in different regions of the FPGA. Finally， if bined global and detailed routing is to be performed， one also specifies: ? the switch block [1] architecture (. how the routing tracks are interconnected)， ? the number of tracks to which each logic block input pin connects (Fc [1])， ? the Fc value for logic block outputs， and ? the