【正文】 出。這種方法的第二個主要優(yōu)點是，如果重復(fù)頻率測量，工具一直 鎖定，頻率測量不重新從頭開始，而是自動驅(qū)使到更低或更高的值。已經(jīng)被指明，在大多數(shù)情況下，對于相同頻率的解決方案，這種方法比傳統(tǒng)方法更快。 儀器的行為和預(yù)期的一樣，和常規(guī)的頻率計數(shù)器工作臺是一樣的。 這些諧波在 DAC 之后將從過濾器刪除。DDS 具有 32 位輸入和一個 12 位輸出的正弦查找表（ LUT）。這次實施的目的是研究該原則的操作方法。三角波形的坡度大小對于常數(shù)輸入頻率是恒定并且取決于 U/ D 轉(zhuǎn)換計數(shù)器（水平軸） 時鐘和 DAC（垂直軸）的電壓基準(zhǔn)。這款 DAC 不會顯示在電路的框圖中。三角波形是 FSW 施加到 DDS 的模擬表示法。這是因為前面提到的滯后作用。 如前所述，這個計數(shù)器的輸出被認(rèn)為是從 FSW 到 DDS 的階段。滯后的時間是可變的。 如果我們考慮到案件中北大學(xué) 2020 屆英文文獻(xiàn)及中文翻譯 第 4 頁 共 6 頁 的 DDS 的頻率等于未知之一，我們會發(fā)現(xiàn)，比較器的輸出將切換，說明或者是DDS 的頻率高于或低于下限未知。 我們將把這個時間稱為“遲滯”。 乍一看人們可以認(rèn)為，合成頻率可達(dá)到實測（鰭），然后計數(shù)器停止運作。鑒 于上述情況，電路操作如下：當(dāng)?shù)谝粋€計數(shù)器（＃ 1）在一個時期內(nèi)遇到 DDS 的兩個未知頻率的上升邊緣，它設(shè)置 RS 觸發(fā)器的輸出。該實現(xiàn)是基于一種改進(jìn)的相位 /頻率比較器，由飛利浦在 74HC4046 PLL 設(shè)備中生產(chǎn) 。 在適當(dāng)?shù)男拚徒獯a后，數(shù)碼的 FSW 被顯示在在一個輸出設(shè)備中，即一臺液晶顯示器或任何其他合適的方式。 此外，該步驟將頻率近似等于 DDS 的最大頻率的 1/ 4。為了克服特定頻率比較器的一些缺點校正階段已被納入。 DDS 的時鐘頻率是非常重要的，因為它減小，該方法的決議（定義為 fclk /）更出色，即它變得更精細(xì)的改進(jìn)。根據(jù)這一點，我們的原型使用一個 33 MHz 的時鐘將有效地數(shù)到 8兆赫。如果 n是增加至 48 個具有相同的時鐘頻率，分辨率為 120 nHz 是可能的 。如果相位步 等于 1，將累加器的計數(shù)加 1，以時鐘周期，以滿足整個 LUT 和生成一個周期的 輸出正弦波。過濾器使數(shù)字化的正弦波更平穩(wěn)，生產(chǎn)連續(xù)輸出信號。 一個典型的頻率設(shè)置字是 32 位寬，但 48 位合成器在較高的頻率分辨率也可使用。一個已知（控制）的頻率波形在電路中產(chǎn)生，并反饋到強制它來接近未知的（輸入）的頻率的頻率比較階段。其他 [46]的內(nèi)容是關(guān)于 微處理器或以微控制器為基礎(chǔ)的。在后一種情況下，代替頻率的周期只是估計的。優(yōu)勢是從 DDS固有的高分辨率和環(huán)路噪聲免疫力而來，從而設(shè)計同樣精確和不受影 響的頻率計。 FC 接受了 DDS 的硬限幅波形以及未知的頻率。s output. This action decreases the frequency of the DDS. At a first glance one could think that the synthesized frequency could reach the measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as hysteresis. Hysteresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous . it can be erroneous. The ambiguity settles when two rising edges of the higher frequency waveform occur during one period of the lower one. If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the parator39。s output instead of the filtered and hard limited waveform because significant jitter will be encountered. The frequency of the output signal for an nbit system is calculated in the following way。 畢業(yè)設(shè)計 說明書 英文文獻(xiàn)及中文翻譯 學(xué)生姓名： 學(xué)號： 學(xué) 院： 專 業(yè)： 指導(dǎo)教師： 2020年 6 月 郭楓 0805074411 信息與通信工程學(xué)院 通信工程 李 沅 An alternative method of precise frequency by the aid of a DDS Contents A method of frequency measurement based on a closed loop posed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DDS) is presented in this paper. The DDS serves as reference sinewave signal generator acting at one of the FC39。s display are presented. 1 Introduction The most monly used frequency measurement technique adopts counters tha t count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency are counted during one or more periods of the unknown one are also mon. In the latter case, the period instead of the frequency is estimated .Some papers in [1] in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (heart) signals (a few hertz) or in the mains frequency (5060 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In [2], the frequency is calculated by the method of lookup tables. Others [46] are microprocessor or microcontroller based. The above methods can be characterized as openloop methods . digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closedloop form characterizes the proposed method in this paper. By the term closedloop we denote some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency parison stage which consecutively forces it to approximate the unknown (