【正文】 ns between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device （ UART） for transmission of error information and munication to controller puter. ? An external realtime clock for data error tag. ? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary. ? A foulup routine to reset program counter if it wanders out of code space. ? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry （ including time tag） was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt – This test used 4 of 6 available interrupt vectors （ Serial, External, Timer0 Overflow, and Timer1 Overflow） to trigger routines that sequentially modified a value in the accumulator which was periodically pared to a known value. Unexpected values were transmitted with register information. Logic – This test performed a series of logic and math putations and provided three types of error identifications: 1） addition/subtraction, 2） logic and 3） multiplication/division. All misputes of putations and expected results were transmitted with other relevant register information. Memory – This test loaded internal data memory at locations D:0x20 through D:0xff （ or D:0x20 through D:0x080 for the Culprit DUT） , indirectly, with an 0x55 pattern. Compares were performed continuously and misputes were corrected while error information and register values were transmitted. Program Counter The program counter was used to continuously fetch constants at various offsets in the code. Constants were pared with known values and misputes were transmitted along with relevant register information. Registers – This test loaded each of four （ 0,1,2,3） banks of generalpurpose registers with either 0xAA （ for banks 0 and 2） or 0x55 （ for banks 1 and 3） . The pattern was alternated in order to test the Program Status Word （ PSW） special function register, which controls generalpurpose register bank selection. Generalpurpose register banks were then pared with their expected values. All misputes were corrected and error information was transmitted. Special Function Registers （ SFR） – This test used learned static values of 12 out 21 available SFRs and then constantly pared the learned value with the current one. Misputes were reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with Boot/Serial Loader code. This code initialized the DUT Computer and interface through a serial connection to the controlling puter, the Test Controller. The DUT Computer downloaded Test Code and put it into Program Code RAM （ located on the Main Board of the DUT Computer） . It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time （ ~10 ms） 。Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller Abstract With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using nondedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects （ SEE） in the space environment. Topics include the types of tests that are required and the design coverage （ ., design libraries: do they need validating for each application?） . Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics （ IAμE） CMOS Ultra Low Power Radiation Tolerant （ Culprit） design is evaluated for SEE mitigative techniques against two mercial 8051 devices. Index Terms Single Event Effects, HardenedByDesign, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiationhardened microelectronic devices that are often two or more generations of performance behind mercial stateoftheart technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of mercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardenedbydesign （ HBD） .Building customtype HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, costeffective, and reliable manner. However, one question still exists: traditional radiationhardened devices have lot and/or wafer radiation qualification tests performed。C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most inst