【正文】 如，如果在電源電壓 的條件下，用測(cè)試芯片靜態(tài)地測(cè)試單粒子效應(yīng)，所測(cè)得的數(shù)據(jù)在電源電壓 操作頻率 100MHz的條件下是否適用？動(dòng)態(tài)因素（即非靜態(tài)操作）包括單粒子瞬變（ SETs）的普及效果 。這是否需要完成輻射條件測(cè)試？回答這個(gè)問(wèn)題之前，先看一下其他的問(wèn)題。通常情況下使用的是 TID（ Co60）和 SEE（重離子和 /或質(zhì)子）來(lái)驗(yàn)證器件。本文所介紹的方法是使用加固微創(chuàng)設(shè)計(jì)技術(shù)的工業(yè)代工。它是評(píng)價(jià)兩個(gè) 8051工業(yè)用設(shè)備單粒子效應(yīng)緩和技術(shù)的一項(xiàng)設(shè)計(jì)。s fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of binational logic （ referred to as ―dual rail design‖） such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated placeandroute of the binatorial logic paths may have placed dual sensitive nodes close enough. At this point, the theory for the Culprit SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough （ and in the right locations） to produce an SET in both halves of the binatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 4060 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this um library, the node separation is several microns. However, since it takes less charge to upset a node operating at Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the perbit memory upset cross section for the Culprit devices and the mercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has bee sensitive to upset. IX. SUMMARY A detailed parison of the SEE sensitivity of a HBD technology （ Culprit） utilizing the 8051 microcontroller as a test vehicle has been pleted. This paper discusses the test methodology used and presents a parison of the mercial versus Culprit technologies based on the data taken. The Culprit devices consistently show significantly higher threshold LETs and an immunity to latch up. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the mercial devices. Additionally, theory is presented, based on the Culprit technology, that explain these results. This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a realworld device structure （ ., not just a test chip） , and paring results to equivalent mercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application. ACKNOWLEDGEMENTS The authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program （ NEPP） , NASA Flight Programs, and the Defense Threat Reduction Agency （ DTRA） . 使用 8051單片機(jī)驗(yàn)證和測(cè)試單粒 子效應(yīng)的加固工藝 摘要 隨著代工業(yè)務(wù)（抗輻射加固設(shè)計(jì)的芯片制造加工廠專門從事的一項(xiàng)業(yè)務(wù)）的減少，使用非專用代工業(yè)務(wù)的新技術(shù)逐步發(fā)展起來(lái)。 the 500 mV and the desired interface voltage. The Culprit C8051 is ROMless and is intended to be instruction set patible with the MSC51 family. V. TEST HARDWARE The 8051 Device Under Test （ DUT） was tested as a ponent of a functional puter. Aside from DUT itself, the other ponents of the DUT puter were removed from the immediate area of the irradiation beam. A small card （ one per DUT package type） with a unique hardwired identifier byte contained the DUT, its crystal, and bypass capacitors （ and voltage level shifters for the Culprit DUTs） . This DUT Board was connected to the Main Board by a short 60conductor ribbon cable. The Main Board had all other ponents required to plete the DUT Computer, including some which nominally are not necessary in some designs （ such as external RAM, external ROM and address latch） . The DUT Computer and the Test Control Computer were connected via a serial cable and munications were established between the two by the Controller （ that runs custom designed serial interface software） . This Controller software allowed for manding of the DUT, downloading DUT Code to the DUT, and realtime error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latch up. VI. TEST SOFTWARE The 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT puter. In this way, individual tests could have been modified at any time without the necessity of burning Proms. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established municatio