【正文】 e pins must have ESD protection structures connected to their bondpads. Some pins can resist ESD and therefore do not require additional protection. Examples include pins connected to substrate and to large diffusions, such as those found in large power transistors. These large junctions may be also to disperse and absorb the ESD energy before it can damage other circuitry. Pins or devices that can withstand ESD events without the addition of ESD protection circuitry are said to be selfprotecting. Pins connecting to relatively small diffusions are vulnerable to ESDinduced junction damage. These junctions are simply not large enough to protect the mselves. Certain junctions, most notably the baseemitter junctions of NPN transistors, are notoriously vulnerable to ESD damage. Avalanching the baseemitter junction of an NPN transistor permanently degrades its beta. A circuit designercan sometimes eliminate the vulnerable junctions by rearranging the circuit. Because ESD vulnerabilities are difficult to predict, cautious designers add protection devices to all pins that might be even remotely vulnerable. Pins that connect only to gates of MOS transistors or to deposited capacitor electrodes are extremely vulnerable to ESD damage. Special input protection structures have been developed to protect dielectrics against HBM and MM events. The extremely high currents characteristic of CDM events require additional protection structures, called CDM clamps, to be placed near the vulnerable devices. The thin emitter oxides employed in some standard bipolar processes are also susceptible to ESDinduced rupture. This vulnerability can be eliminated by ensuring that leads that connect to external bondpads do not cross any emitter region to which they do not connect. Alternatively, ESD structures similar to those used for protecting gates can protect the vulnerable circuits. Most modern versions of the standard bipolar process employ thick emitter oxides, which eliminate the need for these precautions. Considerable ingenuity is often required to formulate successful ESD structures for analog integrated circuits. A dozen or more protection circuits are often required to satisfy the large range of voltages and the many types of vulnerable devices found in analog circuits. The protection devices must also be evaluated to ensure that they do not interfere with the operation of the circuits they protect. The Antenna Effect Dry etching is known to deposit charges upon the surface of the wafer. Exposed conductors can collect an electrical charge that can damage thin gate dielectrics. This failure mechanism is called process plasmainduced damage, or, more colorfully , the antenna effect. The antenna effect generates stressinduced leakage currents that can lead to either immediate or delayed failure of the overstressed dielectrics. Effects The exact source of the electrical charges responsible for the antenna effect is a matter of some controversy. The plasma itself contains an equal number of positive and negative particles. However, various mechanisms can cause local fluctuations in charge densities due to reactor design and AC plasma excitation, and an effect called electron shading, in which adjacent geometries block the isotropic electron flux to a greater degree than they block the anisotropic ion flux. Regardless of the precise mechanisms involved, experience has shown that both dry etching of the precise mechanisms involved experience has shown that both dry etching of conductor layers and the subsequent ash of photoresist can cause plasmainduced damage. The impact of the antenna effect must be evaluated for the etching and ashof each conductor layer. Consider the case of polysilicon. During the initial stages of poly etching the entire surface of the wafer is covered by an unbroken sheet of ploy. Charge reach this ploy plate through all of the openings in the photoresist. Apparently, the fluctuations responsible for the antenna effect largely cancel one another out across the width of the water,for little damage occurs at this point. Partway through the etch process,the individual poly geometries separate from one another. Each geometry now picks up charge around its periphery, where the poly is exposed to the plasma. This charge is injected through the thin gate oxide. The vulnerability of a given geometry to the antenna effect therefore depends upon the ratio of its total perimeter to the active gate area beneath it. The larger this peripheral antenna ratio, the greater the risk of plasmainduced damage. Most processes define a maximum allowed peripheral antenna ratio for poly。 for example, three positive and three negative. After ESD stressing is plete, the part is tested to see if it still meets electrical specifications. Modern integrated circuits are routinely expected to survive 2KV HBM. Specific pins on certain parts may be required to survive up 25KV HBM. Figure shows the circuit employed for the machine model(MM). A 200pF capacitor charged to a specified voltage discharges through a series inductance into the DUT. As in the HBM test, each pin bination is subjected to a predetermined series of positive and negative only a small inductance to limit the peak current, the machine model forms a much harsher test than the human body model. New parts can survive more than 500V under machine model testing. H?50DUTpF200V Figure 2 Machine model A third ESD test called the charged device model(CDM) is gradually replacing the machine model. The charged device model places the integrated circuit package upsidedown on a grounded metal plate and then charges the devices to a specified voltage through a highvalue resistor. A special probe then discharges one pin to a lowimpedance ground. Researc