【正文】 ght. Tb : If you reduce the binational delay (between the Flops of violated path) such a way that T Tcq + Tb + Tsetup Tskew will bee T = Tcq + Tb + Tsetup Tskew. So, the SETUP violation is avoided. How do u reduce the binational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine. Tskew: If u increase the skew, u can change T Tcq + Tb + Tsetup Tskew to T = Tcq + Tb + Tsetup Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing. Case2: After the CHIP is manufatured and is in your hand. In this case, one cannot access the Tb and Tskew. Only the variable that can handle is T. So, Just reduce the frequency (T) such that the violated equation, T Tcq + Tb + Tsetup Tskew bees violation free equation T = Tcq + Tb + Tsetup Tskew. So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency. For HOLD, Thold + Tskew = Tcq + Tb If you have setup time means u r violating the above rule. some how the equation bees Thold + Tskew Tcq + Tb and ur aim is to make Thold + Tskew = Tcq + Tb Now let us consider two cases. Case1: During the Design development phase itself. You have two variables in hand (Tb, Tskew) to avoid HOLD violations. Tb: Increase the Tb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew Tcq + Tb to Thold + Tskew = Tcq + Tb. But this might effect the SETUP time as you are increasing the delay of binational path. So this may not be the perfect solution always. Tskew : Reduce the clock skew so that you will land on Thold + Tskew = Tcq + Tb. To reduce the clock skew, the best solution is to take the help of your PNR engineer. Case2: After the CHIP is manufatured and is in your hand. Do you see any variables that will fix the hold violations after manufaturing?????!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioning chips to the customers. So becareful with the HOLD violations. Note: One can get those equations if u put the those scenarios on a paper and develop the timing diagrams. Hope I39。 QUOTE:Setup time is the minimum time prior totrigerring edge of the clock pulse upto which the data should be kept stable atthe flipflop input so that data could be properly sensed at the is the minimum time after the clock edge upto which the data should bekept stable in order to trigger the flip flop at right voltage level. Setuptime is required in order to find the maximum clock frequency of a circuit.QUOTE:Setup time :It is theminimum time before the clock edge the input should be is due tothe input capacitance present at the takes some time to charge to theparticular logic level at the input.Hold time:It is theminimum time the input should be present stable after the clock isthe time taken for the various switching elements to transit from saturation tocut off and vice versa.So basically set up andhold time is the window during which the input should be changes inthe input during the window period may lead to voltage levels which is notrecognised by the subsequent stages and the circuit may go to metastable stage.QUOTE:suppose ur flipflop is positive edge triggered. timefor which data should be stable prior to positive edge clock is called setuptime constraint .Time for which datashould be stable after the positive edge of clock is called as hold timeconstraint.if any of theseconstraints are violated then flipflop will enter in meta stable state, inwhich we cannot determine the output of flipflop.there are two equation:1. Tcq + Tb Tskew+ Thold2. Tcq + TbTskew+T TsetupTcq is time delay whendata enters the flipflop and data es at output of flip flop.Tb is the logic delaybetween two flip flop.Tskew is the delay ofclock to flip flop: suppose there are two flip flop ,if clock reaches first tosource flip flop and then after some delay to destination flip flop ,it ispositive skew and if vice versa then negative skew.so if u take 2 eq youwill see that setup time is the determining factor of clock39。 由于一般同步電路都不止一級(jí)鎖存（如圖8），而要使電路穩(wěn)定工作，時(shí)鐘周期必須滿足最大延時(shí)要求，縮短最長延時(shí)路徑，才可提高電路的工作頻率。它們的走線時(shí)延的關(guān)系如下：同一個(gè)LAB中（最快） 同列或者同行 不同行且不同列。為了達(dá)到減小T2在設(shè)計(jì)中可以用下面不同的幾種方法綜合來實(shí)現(xiàn)。 從上面的分析可以看出同步系統(tǒng)時(shí)對(duì)D2建立時(shí)間T3的要求為：TTcoT2max＝T3 綜上所述，如果不考慮時(shí)鐘的延時(shí)那么只需關(guān)心建立時(shí)間，如果考慮時(shí)鐘的延時(shí)那么更需關(guān)心保持時(shí)間。 由于建立時(shí)間與保持時(shí)間的和是穩(wěn)定的一個(gè)時(shí)鐘周期，如果時(shí)鐘有延時(shí)，同時(shí)數(shù)據(jù)的延時(shí)也較小那么建立時(shí)間必然是增大的，保持時(shí)間就會(huì)隨之減小，如果減小到不滿足D2的保持時(shí)間要求時(shí)就不能采集到正確的數(shù)據(jù)，如圖6所示。圖5 時(shí)鐘存在延時(shí)但滿足時(shí)序 圖4 組合邏輯的延時(shí)過大時(shí)序不滿足要求 圖3 符合要求的時(shí)序圖 這個(gè)問題是在設(shè)計(jì)中必須考慮的問題，只有弄清了這個(gè)問題才能保證所設(shè)計(jì)的組合邏輯的延時(shí)是否滿足了要求。圖2為統(tǒng)一采用一個(gè)時(shí)鐘的同步設(shè)計(jì)中一個(gè)基本的模型。 在FPGA設(shè)計(jì)的同一個(gè)模塊中常常是包含組合邏輯與時(shí)序邏輯，為了保證在這些邏輯的接口處數(shù)據(jù)能穩(wěn)定的被處理，那么對(duì)建立時(shí)間與保持時(shí)間建立清晰的概念非常重要。 建立時(shí)間（Tsu：set uptime）是指在時(shí)鐘沿到來之前數(shù)據(jù)從不穩(wěn)定到穩(wěn)定所需的時(shí)間，如果建立的時(shí)間不滿足要求那么數(shù)據(jù)將不能在這個(gè)時(shí)鐘上升沿被穩(wěn)定的打入觸發(fā)器；保持時(shí)間（Th：holdtime）是指數(shù)據(jù)穩(wěn)定后保持的時(shí)間，如果保持時(shí)間不滿足要求那么數(shù)據(jù)同樣也不能被穩(wěn)定的打入觸發(fā)器。同樣的可以解釋負(fù)的hold time。討論一下setup time violation 的形成因?yàn)樾盘?hào)比clock 后到達(dá)DFF,或者說到達(dá)的時(shí)間太晚了，這個(gè)時(shí)候這個(gè)DFF就沒有辦法采樣到這個(gè)信號(hào)，于是就出現(xiàn)了setup slak。只有slack是正值，才是好的結(jié)果。、Clock Hold ：39。相對(duì)的保持時(shí)間實(shí)際就是路徑的總延時(shí)（Tco1＋T1）。不考慮CLOCKSKEW情況下。那么 Tsetup2 Tc（CLOCK 周期)－（Tco1＋T1）。 maxbird在該部分詳細(xì)說明了建立時(shí)間和保持時(shí)間的概念，以及如果不滿足二者可能導(dǎo)致的亞穩(wěn)態(tài)的傳播。兩級(jí)觸發(fā)器可防止亞穩(wěn)態(tài)傳播的原理：假設(shè)第一級(jí)觸發(fā)器的輸入不滿足其建立保持時(shí)間，它在第一個(gè)脈沖沿到來后輸出的數(shù)據(jù)就為亞穩(wěn)態(tài)，那么在下一個(gè)脈沖沿到來之前，其輸出的亞穩(wěn)態(tài)數(shù)據(jù)在一段恢復(fù)時(shí)間后必須穩(wěn)定下來，而且穩(wěn)定的數(shù)據(jù)必須滿足第二級(jí)觸發(fā)器的建立時(shí)間，如