【正文】 channel width. You will notice that the higher the frequency deviation, the greater bandwidth that the channel occupies. Below, we show a FM signal with a carrier of 1 MHz and a frequncy deviation of 500 KHz. As you can observe from the graph below, the modulated signal occupies over 1 MHz of bandwidthConclusion:Frequency Modulation (FM) is an important modulation scheme both because of its widespread mercial use, and because of its simplicity. As we have seen in this document, frequency modulation can be simplified to phase modulation with a simple integrator. As a result, frequency modulated signals can be generated with the National Instruments vector signal generator, because they require nothing more than an IQ modulator.References:1) Simon Haykin, Communications Systems. 2) . Lathi, Modern Digital and Analog Communications Systems.英文文獻(xiàn)2Amplitude Shift Keying: Step by StepIntroduction:This stepbystep demo is designed to examine the Amplitude Shift Keying (ASK) digital modulation scheme. Fundamentally, digital modulation requires changing characteristics of the carrier wave over time. Each change results in a sine wave with a different phase, amplitude, or frequency than before. As a result, different “states” of the sine wave are referred to as symbols which represent some digital bit pattern. In this exercise, we will construct a LabVIEW VI that transmits and receives a digital bit stream in software using ASK.Background:Below is a plot that shows the transmitted signal for 8ASK. Here the amplitude level of the carrier signal represents 3bits of digital data. Zero amplitude represents 000 , and the highest amplitude represents 111. The other levels are at intervals between. Programming:Open “Simple_ASK_Transceiver(Simulated).vi” and inspect the front panel. It allows the user to choose the number of symbols that will be used (MASK), pulse shaping filter, symbol rate, and carrier rate. Additionally, there is a control for the amount of simulated channel noise in this system. There is a Tab Control which shows graphs of the raw and modulated waveforms on one tab and the constellation plot on the other (which is ideally a single line with ASK).The block diagram consists of a while loop that will iterate once every 100 milliseconds. Inside this loop, we will generate, modulate, demodulate and display digital data.1) Place a “Generate System Parameters” VI on the block diagram and select the polymorphic instance ASK (M). Connect the wire ing from the MASK control to the corresponding input terminal on this VI. This VI will create an ASK symbol map based on the MASK value selected on the front panel.2) Place an “MT Bit Generation” VI on the block diagram and wire the output of the multiplication function to the total bits input. This VI will generate a digital bit stream that will later be modulated using ASK.3) Place a “Generate Filter Coefficients” VI on the block diagram. Right click on the modulation type terminal and create a constant, then select ASK. Wire the pulse shaping filter control into the appropriate input. This VI will generate filter coefficients that will be used during modulation to reduce the bandwidth of the modulated signal.4) Place a “Modulate ASK” VI on the block diagram and wire in the system parameters, bit stream, and pulse shaping coefficients from the three previous VIs. Also wire the Boolean value from the Reset Control into reset? input. This VI will perform APSK modulation on the input bit stream using the system parameters and filter coefficients specified.5) Place an “Add AWGN” VI on the block diagram and wire the Noise Impairments control to the Eb/N0 input. Also wire the Boolean value from the Reset Control into the reset? input. This VI will subject the modulated signal to Additive White Gaussian Noise based on the “noise impairments” control on the front panel.6) Place a “Demodulate ASK” VI on the block diagram and wire the system parameters, filter coefficients and input plex waveform form previous VIs. Also wire the Boolean value from the Reset Control into the reset? input. This VI will demodulate the input signal and return the recovered bit stream.Finally, wire the error out of each VI to the error in of the next to handle any errors that occur and enforce dataflow between the VIs. Return to the front panel and run the VI to see ASK modulation in action. Experiment with the ASK (M), pulse shaping filter, and Noise impairments controls. This simple transceiver demonstrates modulation and demodulation using Amplitude Shift Keying. 譯文1 頻率調(diào)制引言：調(diào)頻（FM）是一種載波頻率的變化直接與基帶信號(hào)中的變化相對(duì)應(yīng)的調(diào)制形式，這被認(rèn)為是一種模擬形式的調(diào)制，因?yàn)榛鶐盘?hào)通常是模擬波形，而不是離散的數(shù)值。其次要感謝論文中參考的參考文獻(xiàn)的作者；感謝對(duì)于提供論文中隱含的上述提及的支持者以及研究思想和設(shè)想的支持者；感謝各大網(wǎng)站平臺(tái)提供的強(qiáng)大的技術(shù)支持。致謝在這里首先要感謝指導(dǎo)老師鄒雪妹老師。此設(shè)計(jì)只能對(duì)15Hz10MHz的頻率進(jìn)行測(cè)量，而不能測(cè)量信號(hào)的占空比，脈寬的測(cè)量。和傳統(tǒng)的頻率計(jì)相比，利用FPGA設(shè)計(jì)的頻率計(jì)簡(jiǎn)化了電路板設(shè)計(jì)，提高了系統(tǒng)設(shè)計(jì)的實(shí)用性和可靠性，實(shí)現(xiàn)數(shù)字系統(tǒng)的軟件化，這也是數(shù)字邏輯設(shè)計(jì)的趨勢(shì)。但當(dāng)設(shè)計(jì)比較復(fù)雜，運(yùn)行頻率比較高的時(shí)候，不做時(shí)序分析，不加上一些必要的約束，就很難保證設(shè)計(jì)能且穩(wěn)定的運(yùn)行在所設(shè)定的頻率上。第四章 總體設(shè)計(jì)驗(yàn)證在Quartus II中將所有功能模塊建立完成后，將各個(gè)模塊在頂層圖形文件中連接起來。雖然8個(gè)LED是依次顯示，但是受視覺分辨率的影響，看到的現(xiàn)象是8個(gè)LED同時(shí)工作。位碼也就是LED的顯示使能端，對(duì)于共陰級(jí)的LED而言，低電平使能。所以yshang=109/8388623=119。這就需要把32位二進(jìn)制轉(zhuǎn)化為8421BCD碼，每4位對(duì)應(yīng)的十進(jìn)制的09。 yyushu = temp_a[63:32]。 //左移一位 if(temp_a[63:32] = tempb) temp_a = temp_a temp_b + 139。 for(i = 0。always (posedge clk)begin temp_a = {3239。 周期模塊封裝圖32位除法器division中的除數(shù)設(shè)置為109，由于本次頻率計(jì)的信號(hào)源頻率范圍是15hz~10MHZ，根據(jù)周期T=1/f（單位：s）可知，當(dāng)除數(shù)取1 的時(shí)候，周期很小，誤差較大；所以在這里除法器中除數(shù)取109時(shí)，此時(shí)周期單位：ns。程序要求只有當(dāng)使能端信號(hào)為高電平時(shí)計(jì)數(shù)器才能正常工作，每個(gè)時(shí)鐘的上升沿到來時(shí)計(jì)數(shù)器加1，因?yàn)檫@里要實(shí)現(xiàn)的是10進(jìn)制計(jì)數(shù)，所以當(dāng)計(jì)數(shù)到10時(shí)計(jì)數(shù)器清零，同時(shí)產(chǎn)生進(jìn)位信號(hào)，這里的進(jìn)位信號(hào)僅為一個(gè)脈沖信號(hào)，一旦計(jì)數(shù)從9變?yōu)?，脈沖信號(hào)立即變?yōu)榈碗娖?。高電平允許計(jì)數(shù)，低電平時(shí)停止計(jì)數(shù)。鎖存輸出并不是立即進(jìn)行的，而是經(jīng)歷了一個(gè)短暫的延時(shí)，這是由于硬件引起的。鎖存器的作用是數(shù)據(jù)保持，它將會(huì)把數(shù)據(jù)保存到下次觸發(fā)或復(fù)位，主要是主從觸發(fā)器組成的。此時(shí)，根據(jù)測(cè)頻的時(shí)序要求，可得出信號(hào)LOAD和CLR_CNT的邏輯描述。確保本設(shè)計(jì)的頻率計(jì)是等精度頻率計(jì)。設(shè)置鎖存器的好處是使顯示的數(shù)據(jù)穩(wěn)定，不會(huì)由于周期性的清零信號(hào)而不斷閃爍。該模塊產(chǎn)生的3個(gè)控制信號(hào)，分別為TSTEN,LOAD,CLR_CNT。 測(cè)頻控制信號(hào)模塊測(cè)頻控制產(chǎn)生器testctl。實(shí)現(xiàn)方法：假設(shè)未按鍵時(shí)輸入1，按