基于fpga的計(jì)數(shù)器設(shè)計(jì)-wenkub
2022-09-08 19:21:55 本頁面
【正文】 ............................ 1 計(jì)數(shù)器的發(fā)展 ................................................................................................................ 1 第 2 章 設(shè)計(jì)環(huán)境 .................................................................................................................... 2 Quartus II .................................................................................................................... 2 軟件簡介 ............................................................................................................ 2 功能 .................................................................................................................... 3 Verilog HDL 硬件描述語言 ....................................................................................... 4 語言簡介 ............................................................................................................ 4 主要能力 ............................................................................................................ 4 語言用途 ............................................................................................................ 6 Verilog HDL 的發(fā)展歷史 .................................................................................. 6 主要應(yīng)用 .............................................................................................................. 7 Electronic Design Automation .................................................................................... 8 第 3 章 設(shè)計(jì)思路 .................................................................................................................. 10 輸入 模塊 .................................................................................................................. 10 寄存器 模塊 ............................................................................................................... 11 輸出 模塊 ................................................................................................................... 11 計(jì)數(shù) 模塊 ................................................................................................................... 11 第 4 章 程序設(shè)計(jì) .................................................................................................................. 13 主程序 ....................................................................................................................... 13 always 語句 ............................................................................................................... 13 ifelse 語句 ................................................................................................................ 13 第 5 章 波形仿真 .................................................................................................................. 14 結(jié)論 .......................................................................................................................................... 15 參考文獻(xiàn) .................................................................................................................................. 16 附錄 1....................................................................................................................................... 17 致謝 .......................................................................................................................................... 18 通信 102班，姓名 青瓜 基于 FPGA的計(jì)數(shù)器 設(shè)計(jì) 1 第 1 章 緒論 計(jì)數(shù)器的種類 如果按照計(jì)數(shù)器中的觸發(fā)器是否同時(shí)翻轉(zhuǎn)分類，可將計(jì)數(shù)器分為 同步計(jì)數(shù)器 和異步計(jì)數(shù)器 兩種。 關(guān)鍵詞 ： 計(jì)數(shù)器 ； VerilogHDL； QuartusⅡ ； FPGA；
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