【正文】 es the SP down one word in RAM (SP=SP2), and puts the value to be pushed at the new SP. Pop does the reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value from the TOS (top of stack) back into the PC. I have one simple rule of thumb for the SP: leave it alone. Set the stack pointer as part of your initialization, and don39。use R12 as we please Rla R12 Rla R12 Mov R12amp。multiply R15 by two,since PC is always even Rla R15 。range checking Jge outofrange 。t know today what the values in R8, R9 and R15 represent. This was code I wrote to quickly validate an algorithm, rather than production code, so I didn39。4xx devices throughout this book. Part Numbering Convention Part numbers for MSP430 devices are determined based on their capabilities. All device part numbers follow the following template: MSP430Mt Fa F bMc M: Memory Type C: ROM F: Flash P: OTP E: EPROM (for developmental use. There are few of these.) F a, F b: Family and Features 10, 11: Basic 12, 13: Hardware UART 14: Hardware UART, Hardware Multiplier 31, 32: LCD Controller 33: LCD Controller, Hardware UART, Hardware Multiplier 41: LCD Controller 43: LCD Controller, Hardware UART 44: LCD Controller, Hardware UART, Hardware Multiplier Mc: Memory Capacity 0: 1kb ROM, 128b RAM 1: 2kb ROM, 128b RAM 2: 4kb ROM, 256b RAM 3: 8kb ROM, 256b RAM 4: 12kb ROM, 512b RAM 5: 16kb ROM, 512b RAM 6: 24kb ROM, 1kb RAM 7: 32kb ROM, 1kb RAM 8: 48kb ROM, 2kb RAM 9: 60kb ROM, 2kb RAM Example: The MSP430F435 is a Flash memory device with an LCD controller, a hardware UART, 16 kb of code memory, and 512 bytes of RAM. The part numbering scheme described above is a bit fragmented. There are mon features not consistently represented (type of ADC, number of timers, etc), and there are some other inconsistencies (for example, the 33 family has the multiplier, but the 13 and 43s do not). I would remend against selecting parts based on their numbering scheme. Rather, once you have a vague idea of your requirements, go to the TI website (), and use their parametric sort feature. Architecture: CPU and Memory As discussed in chapter 1, the MSP430 utilizes a 16bit RISC architecture, which is capable of processing instructions on either bytes or words. The CPU is identical for all members of the 39。430 is petitive in price with the 8bit controller market, and supports both 8 and 16bit instructions, allowing migration from most similarly sized platforms. The family of devices ranges from the very small (1k ROM, 128 bytes for RAM, subdollar) up to larger (60k ROM, 2k RAM, with prices in the $10 range) devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is a basic unit, the MSP430x1xx, which is a more featurerich family, and the MSP430x4xx, which is similar to the 39。1xx, with a built in LCD driver. You will find these referred to as 39。430 family. It consists of a 3stage instruction pipeline, instruction decoding, a 16bit ALU, four dedicateduse registers, and twelve working (or scratchpad) registers. The CPU is connected to its memory through two 16bit busses, one for addressing, and the other for data. All memory, including RAM, ROM, information memory, special function registers, and peripheral registers are mapped into a single, contiguous address space. This architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains available for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented. Second, there are plenty of working registers. After years of having one or two working registers, I greatly enjoyed my first experience with the twelve 16bit CPU scratchpads. The programming style is slightly different, and can be much more efficient, especially in the hands of a programmer who knows how to use this feature to its fullest. Third, this architecture is deceptively straightforward. It is very flexible, and the addressing modes are more plicated than most other small processors. But, beyond that, this architecture is simple, efficient and clean. There are two busses, a single linear memory space, a rather vanilla processor core, and all peripherals are memorymapped. CPU Features The ALU The 39。t document it sufficiently. Now, it is relative gibberish. Don39。if R157,do not use PC switch Cmp 0,R15 。double R15again,since symbolic jmp is 2 words long Add R15,PC 。BAR 。t fiddle with it manually after that. As long as you are wary of two stack conditions, the stack pointer manages itself. These two conditions are: Asymmetric push/pop binations. Every push should have a pop. If you push a bunch of variables, and fail to pop them back out, it will e back to haunt you. If you pop an empty stack, the SP moves out of RAM, and the program will fail. Stack encroachment. Remember, the stack is implemented in RAM. If your program has multiple interrupts, subroutine calls, or manual pushes, the stack will take up more RAM, potentially overwriting values your code needs elsewhere. Memory Structure Special Function Registers Special function registers are, as you might have guessed, memorymapped registers with speci