【正文】 power, feature rich 16bit microcontrollers from Texas Instruments. They share a mon, RISCtype, Neumann CPU core. The 39。430 is petitive in price with the 8bit controller market, and supports both 8 and 16bit instructions, allowing migration from most similarly sized platforms. The family of devices ranges from the very small (1k ROM, 128 bytes for RAM, subdollar) up to larger (60k ROM, 2k RAM, with prices in the $10 range) devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is a basic unit, the MSP430x1xx, which is a more featurerich family, and the MSP430x4xx, which is similar to the 39。1xx, 39。4xx devices throughout this book. Part Numbering Convention Part numbers for MSP430 devices are determined based on their capabilities. All device part numbers follow the following template: MSP430Mt Fa F bMc M: Memory Type C: ROM F: Flash P: OTP E: EPROM (for developmental use. There are few of these.) F a, F b: Family and Features 10, 11: Basic 12, 13: Hardware UART 14: Hardware UART, Hardware Multiplier 31, 32: LCD Controller 33: LCD Controller, Hardware UART, Hardware Multiplier 41: LCD Controller 43: LCD Controller, Hardware UART 44: LCD Controller, Hardware UART, Hardware Multiplier Mc: Memory Capacity 0: 1kb ROM, 128b RAM 1: 2kb ROM, 128b RAM 2: 4kb ROM, 256b RAM 3: 8kb ROM, 256b RAM 4: 12kb ROM, 512b RAM 5: 16kb ROM, 512b RAM 6: 24kb ROM, 1kb RAM 7: 32kb ROM, 1kb RAM 8: 48kb ROM, 2kb RAM 9: 60kb ROM, 2kb RAM Example: The MSP430F435 is a Flash memory device with an LCD controller, a hardware UART, 16 kb of code memory, and 512 bytes of RAM. The part numbering scheme described above is a bit fragmented. There are mon features not consistently represented (type of ADC, number of timers, etc), and there are some other inconsistencies (for example, the 33 family has the multiplier, but the 13 and 43s do not). I would remend against selecting parts based on their numbering scheme. Rather, once you have a vague idea of your requirements, go to the TI website (), and use their parametric sort feature. Architecture: CPU and Memory As discussed in chapter 1, the MSP430 utilizes a 16bit RISC architecture, which is capable of processing instructions on either bytes or words. The CPU is identical for all members of the 39。430 processor includes a pretty typical ALU (arithmetic logic unit). The ALU handles addition, subtraction, parison and logical (AND, OR, XOR) operations. ALU operations can affect the overflow, zero, negative, and carry flags. The hardware multiplier, which is not available in all devices, is implemented as a peripheral device, and is not part of the ALU (see Chapter 6). Working Registers The 39。t know today what the values in R8, R9 and R15 represent. This was code I wrote to quickly validate an algorithm, rather than production code, so I didn39。t let this happen to you. No matter how obvious or trivial register use seems, document it anyway. Constant Generators R2 and R3 function as constant generators, so that register mode ma y be used instead of immediate mode for some mon constants. (R2 is a dual use register. It serves as the Status Register, as well.) Generated constants include some mon singlebit values (0001h, 0002h, 0004h, and 0008h), zero (0000h), and an all 1s field (0FFFFh). Generation is based on the W(S) value in the instruction word, and is described by the table below. W(S) value in R2 value in R3 00 ———— 0000h 01 (0) (absolute mode) 0001h 10 0004h 0002h 11 0008h 0FFFFh Program Counter The Program Counter is located in R0. Since individual memory location addresses are 8bit, but all instructions are 16 bit, the PC is constrained to even numbers (. the LSB of the PC is always zero). Generally speaking, it is best to avoid direct manipulation of the PC. One exception to this rule of thumb is the implementation of a switch, where the code jumps to a spot, dependent on a given value. (., if value=0, jump to location0, if value=1, jump to location1, etc.) This process is shown in Example . Example Switch Statement via Manual PC Control Mov value,R15 。range checking Jge outofrange 。more range checking Jn outofrange 。multiply R15 by two,since PC is always even Rla R15 。PC goes to proper jump Jmp value0 Jmp value1 Jmp value2 Jmp value3 Jmp value4 Jmp value5 Jmp value6 Jmp value7 Outofrange Jmp RangeError This is a relatively mon approach, and most C pilers will implement switch statements with something similar. When implementing this manually (., in assembly language), the programmer needs to keep several things in mind: Always do proper range checking. In the example, we checked for conditions outside both ends of the valid range. If this is not performed correctly, the code can jump to an unintended location. Pay close attention to the addressing modes of the jump statements. The second doubling of R15, prior to the add statement, is added because the jump statement requires two words when symbolic mode addressing is used. Be careful that none of your interrupt handlers have the potential to affect your value register (R15 in the example). If the interrupt handler needs to use one of these registers, the handler needs to store the value to RAM first. The most mon procedure is to push the register to the stack at the beginning of the IS