外文翻譯---具有8kb 系統(tǒng)可編程 flash 的8位微控制器-文庫吧
2025-01-02 23:07 本頁面
【正文】 uation kits.The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security.When an interrupt occurs, the Global Interrupt Enable Ibit is cleared and all interrupts are disabled. The user software can write logic one to the Ibit to enable nested enabled interrupts can then interrupt the current interrupt routine. The Ibit is automatically set when a Return from Interrupt instruction – RETI – is executed.There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.The second type of interrupts will trigger as long as the interrupt condition is interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is that the Status Register is not automatically stored when entering an interrupt routine,nor restored when returning from an interrupt routine. This must be handled by software.When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycl
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