【正文】 tions until the next Interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer andADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal resonator Oscillator is running while the rest of the device is sleeping. This allows very fast startup bined with lowpower consumption.The device is manufactured using Atmel’s high density nonvolatile memory Flash Program memory can be reprogrammed InSystem through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an Onchip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true ReadWhileWrite operation. By bining an 8bit RISC CPU with InSystem SelfProgrammable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highlyflexible and costeffective solution to many embedded control applications.The ATmega8 AVR is supported with a full suite of program and system development tools, including C pilers, macro assemblers, program debugger/simulators, InCircuit Emulators, and evaluation kits.The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security.When an interrupt occurs, the Global Interrupt Enable Ibit is cleared and all interrupts are disabled. The user software can write logic one to the Ibit to enable nested enabled interrupts can then interrupt the current interrupt routine. The Ibit is automatically set when a Return from Interrupt instruction – RETI – is executed.There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt cond